Patents by Inventor Neeraj Shrivastava
Neeraj Shrivastava has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11881867Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.Type: GrantFiled: September 7, 2021Date of Patent: January 23, 2024Assignee: Texas Instruments IncorporatedInventors: Narasimhan Rajagopal, Eeshan Miglani, Chirag Chandrahas Shetty, Neeraj Shrivastava, Shagun Dusad, Srinivas Kumar Reddy Naru, Nithin Gopinath, Charls Babu, Shivam Srivastava, Viswanathan Nagarajan, Jagannathan Venkataraman, Harshit Moondra, Prasanth K, Visvesvaraya Appala Pentakota
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Publication number: 20230387932Abstract: A circuit includes a nonlinear analog-to-digital converter (ADC) configured to provide a first digital output based on an analog input signal. The circuit also includes a linearization circuit having a lookup table (LUT) memory configured to store initial calibration data. The linearization circuit is coupled to the nonlinear ADC and is configured to: determine updated calibration data based on the initial calibration data; replace the initial calibration data in the LUT memory with the updated calibration data; and provide a second digital output at a linearization circuit output of the linearization circuit based on the first digital output and the updated calibration data.Type: ApplicationFiled: May 26, 2022Publication date: November 30, 2023Inventors: Narasimhan RAJAGOPAL, Nithin GOPINATH, Viswanathan NAGARAJAN, Neeraj SHRIVASTAVA, Visvesvaraya A. PENTAKOTA, Harshit MOONDRA, Abhinav CHANDRA
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Publication number: 20230344436Abstract: An analog-to-digital converter circuit module utilizing dither to reduce multiplicative noise. A dither generation circuit generates a noise-shaped analog dither signal having lower amplitudes at frequencies below a cutoff frequency than at frequencies above the cutoff frequency. The noise-shaped analog dither signal is added to the input analog signal to be converted and the summed signal applied to an analog-to-digital converter The dither generation circuit may be implemented as an analog dither generator followed by an analog high-pass filter. The dither generation circuit may alternatively be implemented digitally, for example with a digital noise-shaping filter applying a high-pass digital filter to a pseudo-random binary sequence. The digital dither generation circuit may alternatively be implemented by one or more 1-bit sigma-delta modulators, each generating a bit of a digital dither sequence that is converted to analog.Type: ApplicationFiled: April 26, 2022Publication date: October 26, 2023Inventors: Nithin Gopinath, Visvesvaraya A. Pentakota, Neeraj Shrivastava, Harshit Moondra
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Patent number: 11438001Abstract: A method of using an analog-to-digital converter system includes receiving a sampled voltage corresponding to one of an input voltage and a known voltage, causing preamplifiers to generate output signals based on the sampled voltage, generating first and second signals based on the output signals, causing a delay-resolving delay-to-digital backend to generate a single-bit digital signal representing an order of receipt of the first and second signals, and adjusting one or more of the preamplifiers based on the digital signal. The disclosure also relates to a system which includes a voltage-to-delay frontend and a delay-resolving backend, and to a method which includes causing a delay comparator to generate a single-bit digital signal representing an order of receipt of input signals, causing the comparator to transmit a residue delay signal to a succeeding comparator, and transmitting a signal to adjust one or more of the preamplifiers based on the digital signal.Type: GrantFiled: December 24, 2020Date of Patent: September 6, 2022Assignee: Texas Instruments IncorporatedInventors: Narasimhan Rajagopal, Chirag Chandrahas Shetty, Neeraj Shrivastava, Prasanth K, Eeshan Miglani
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Publication number: 20220247421Abstract: In described examples, a circuit includes a multiplexer. The multiplexer receives an input voltage and a calibration signal. An analog-to-digital converter (ADC) is coupled to the multiplexer and generates an output code in response to the calibration signal. A storage circuit is coupled to the ADC and stores the input code representative of the calibration signal at an address corresponding to the output code. The stored input code includes an index value and a coarse value.Type: ApplicationFiled: January 31, 2022Publication date: August 4, 2022Inventors: Visvesvaraya Appala Pentakota, Srinivas Kumar Reddy Naru, Chirag Shetty, Eeshan Miglani, Neeraj Shrivastava, Narasimhan Rajagopal, Shagun Dusad
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Publication number: 20220247420Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.Type: ApplicationFiled: September 7, 2021Publication date: August 4, 2022Inventors: Narasimhan Rajagopal, Eeshan Miglani, Chirag Chandrahas Shetty, Neeraj Shrivastava, Shagun Dusad, Srinivas Kumar Reddy Naru, Nithin Gopinath, Charls Babu, Shivam Srivastava, Viswanathan Nagarajan, Jagannathan Venkataraman, Harshit Moondra, Prasanth K, Visvesvaraya Appala Pentakota
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Publication number: 20220209782Abstract: A method of using an analog-to-digital converter system includes receiving a sampled voltage corresponding to one of an input voltage and a known voltage, causing preamplifiers to generate output signals based on the sampled voltage, generating first and second signals based on the output signals, causing a delay-resolving delay-to-digital backend to generate a single-bit digital signal representing an order of receipt of the first and second signals, and adjusting one or more of the preamplifiers based on the digital signal. The disclosure also relates to a system which includes a voltage-to-delay frontend and a delay-resolving backend, and to a method which includes causing a delay comparator to generate a single-bit digital signal representing an order of receipt of input signals, causing the comparator to transmit a residue delay signal to a succeeding comparator, and transmitting a signal to adjust one or more of the preamplifiers based on the digital signal.Type: ApplicationFiled: December 24, 2020Publication date: June 30, 2022Inventors: Narasimhan RAJAGOPAL, Chirag Chandrahas SHETTY, Neeraj SHRIVASTAVA, Prasanth K, Eeshan MIGLANI
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Patent number: 11316525Abstract: An analog-to-digital converter system includes a digital-to-analog converter for generating calibration voltages based on digital input codes, and an analog-to-digital converter, connected to the digital-to-analog converter, for receiving the calibration voltages from the digital-to-analog converter, for receiving sampled voltages, for generating digital output codes based on the calibration voltages, and for generating digital output codes based on the sampled voltages. The analog-to-digital converter system may have a lookup table, connected to the analog-to-digital converter, for storing the first digital output codes in association with the digital input codes. A method of calibrating an analog-to-digital converter system is also disclosed.Type: GrantFiled: January 26, 2021Date of Patent: April 26, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Visvesvaraya Appala Pentakota, Narasimhan Rajagopal, Chirag Chandrahas Shetty, Prasanth K, Neeraj Shrivastava, Eeshan Miglani, Jagannathan Venkataraman
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Patent number: 11239854Abstract: A non-linearity correction circuit includes a non-linearity coefficient estimation circuit. The non-linearity coefficient estimation circuit includes a data capture circuit, a non-linearity term generation circuit, a time-to-frequency conversion circuit, a bin identification circuit, a residual non-linearity conversion circuit, and a non-linearity coefficient generation circuit. The non-linearity term generation circuit is coupled to the data capture circuit. The time-to-frequency conversion circuit is coupled to the data capture circuit and the non-linearity term generation circuit. The bin identification circuit is coupled to the time-to-frequency conversion circuit. The residual non-linearity conversion circuit is coupled to the bin identification circuit. The non-linearity coefficient generation circuit is coupled to the bin identification circuit and the residual non-linearity conversion circuit.Type: GrantFiled: October 2, 2020Date of Patent: February 1, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jawaharlal Tangudu, Pankaj Gupta, Sreenath Narayanan Potty, Ajai Paulose, Chandrasekhar Sriram, Mahesh Ravi Varma, Shabbar Abbasi Vejlani, Neeraj Shrivastava, Himanshu Varshney, Divyeshkumar Mahendrabhai Patel, Raju Kharataram Chaudhari
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Publication number: 20210105021Abstract: A non-linearity correction circuit includes a non-linearity coefficient estimation circuit. The non-linearity coefficient estimation circuit includes a data capture circuit, a non-linearity term generation circuit, a time-to-frequency conversion circuit, a bin identification circuit, a residual non-linearity conversion circuit, and a non-linearity coefficient generation circuit. The non-linearity term generation circuit is coupled to the data capture circuit. The time-to-frequency conversion circuit is coupled to the data capture circuit and the non-linearity term generation circuit. The bin identification circuit is coupled to the time-to-frequency conversion circuit. The residual non-linearity conversion circuit is coupled to the bin identification circuit. The non-linearity coefficient generation circuit is coupled to the bin identification circuit and the residual non-linearity conversion circuit.Type: ApplicationFiled: October 2, 2020Publication date: April 8, 2021Inventors: Jawaharlal TANGUDU, Pankaj GUPTA, Sreenath Narayanan POTTY, Ajai PAULOSE, Chandrasekhar SRIRAM, Mahesh Ravi VARMA, Shabbar Abbasi VEJLANI, Neeraj SHRIVASTAVA, Himanshu VARSHNEY, Divyeshkumar Mahendrabhai PATEL, Raju Kharataram CHAUDHARI
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Publication number: 20210091778Abstract: In described examples, a switched capacitor circuit includes an amplifier that generates a first output signal in response to a first sampled input signal. A second sampling circuit is coupled to the amplifier and generates an output signal in response to the first output signal. A first current boost circuit is coupled to the amplifier and the second sampling circuit and provides current to the second sampling circuit when the first output signal is below a first threshold. A second current boost circuit is coupled to the amplifier and the second sampling circuit and receives current from the second sampling circuit when the first output signal is above a second threshold.Type: ApplicationFiled: September 19, 2019Publication date: March 25, 2021Inventors: Neeraj Shrivastava, Sai Aditya Nurani
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Patent number: 10930362Abstract: A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.Type: GrantFiled: June 30, 2020Date of Patent: February 23, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Aravind Ganesan, Jaiganesh Balakrishnan, Nagarajan Viswanathan, Yeswanth Guntupalli, Ajai Paulose, Mathews John, Jagannathan Venkataraman, Neeraj Shrivastava
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Publication number: 20200327950Abstract: A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.Type: ApplicationFiled: June 30, 2020Publication date: October 15, 2020Inventors: Aravind GANESAN, Jaiganesh BALAKRISHNAN, Nagarajan VISWANATHAN, Yeswanth GUNTUPALLI, Ajai PAULOSE, Mathews JOHN, Jagannathan VENKATARAMAN, Neeraj SHRIVASTAVA
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Patent number: 10741268Abstract: A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.Type: GrantFiled: December 28, 2018Date of Patent: August 11, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Aravind Ganesan, Jaiganesh Balakrishnan, Nagarajan Viswanathan, Yeswanth Guntupalli, Ajai Paulose, Mathews John, Jagannathan Venkataraman, Neeraj Shrivastava
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Publication number: 20200212921Abstract: A top-plate sampling analog-to-digital converter (ADC) circuit includes a first ADC stage and a residue amplifier coupled to the first ADC stage. The residue amplifier comprises a first transistor with a control terminal, a first current terminal, and a second current terminal. The residue amplifier also comprises a second transistor with a control terminal, a first current terminal, and a second current terminal. The residue amplifier also comprises a linearity adjustment circuit coupled to a second current terminal of at least one of the first transistor and the second transistor. The linearity adjustment circuit comprises at least one switch that changes its state as a function of an input sampling phase and a gain phase of the residue amplifier.Type: ApplicationFiled: December 28, 2018Publication date: July 2, 2020Inventors: Sai Aditya KrishnaSwamy NURANI, Arun MOHAN, Shagun DUSAD, Neeraj SHRIVASTAVA
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Patent number: 10686461Abstract: A top-plate sampling analog-to-digital converter (ADC) circuit includes a first ADC stage and a residue amplifier coupled to the first ADC stage. The residue amplifier comprises a first transistor with a control terminal, a first current terminal, and a second current terminal. The residue amplifier also comprises a second transistor with a control terminal, a first current terminal, and a second current terminal. The residue amplifier also comprises a linearity adjustment circuit coupled to a second current terminal of at least one of the first transistor and the second transistor. The linearity adjustment circuit comprises at least one switch that changes its state as a function of an input sampling phase and a gain phase of the residue amplifier.Type: GrantFiled: December 28, 2018Date of Patent: June 16, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sai Aditya KrishnaSwamy Nurani, Arun Mohan, Shagun Dusad, Neeraj Shrivastava
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Publication number: 20200152284Abstract: A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.Type: ApplicationFiled: December 28, 2018Publication date: May 14, 2020Inventors: Aravind GANESAN, Jaiganesh BALAKRISHNAN, Nagarajan VISWANATHAN, Yeswanth GUNTUPALLI, Ajai PAULOSE, Mathews JOHN, Jagannathan VENKATARAMAN, Neeraj SHRIVASTAVA
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Patent number: 10644714Abstract: An analog-to-digital converter including a first stage and a second stage. The first stage includes a first sample-and-hold (SH) having an input coupled to a voltage input node of the ADC, and having a first SH output. The first stage also includes a buffer, a first flash converter and a first digital-to-analog converter (DAC). The buffer has an input coupled to the first SH output and has a buffer output. The first flash converter has an input coupled to the first SH output, and has a first flash converter output. The first DAC has an input coupled to the first flash converter output. The second stage includes a second flash converter having an input coupled to the buffer output.Type: GrantFiled: March 19, 2019Date of Patent: May 5, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Arun Mohan, Neeraj Shrivastava
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Publication number: 20190363679Abstract: In some examples, an amplifier stage includes a voltage-gain amplifier stage and a negative capacitance circuit coupled to the voltage-gain amplifier stage, the negative capacitance circuit comprising a first transistor that provides a first temperature-biased current.Type: ApplicationFiled: August 12, 2019Publication date: November 28, 2019Inventors: Ani XAVIER, Neeraj SHRIVASTAVA, Arun MOHAN, Shagun DUSAD
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Patent number: 10476542Abstract: A digital step attenuator (DSA) includes a switch control circuit which receives the attenuated signal output by the DSA from a buffer and generates a tracked control signal for switches within the DSA. Some switch control circuits include a capacitor coupled to receive the buffered signal, a supply voltage, and a switch control logic sub-circuit for each switch. Each switch control logic sub-circuit receives a control signal, for either the gate or the bulk terminal of the switch, and generates the tracked control signal. In other embodiments, switch control circuits include a complementary MOSFET switching device coupled to receive a control signal, and a capacitor coupled to receive the buffered signal, both of which are connected to an output terminal for the tracked control signal. In those embodiments, the DSA includes a switch control circuit for each switch connected to the DSA output.Type: GrantFiled: February 13, 2019Date of Patent: November 12, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Neeraj Shrivastava, Rajendrakumar Joish, Shagun Dusad, Visvesvaraya Pentakota