Patents by Inventor Neerav Parikh

Neerav Parikh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ZERO COPY HOST INTERFACE IN A SCALABLE INPUT/OUTPUT (I/O) VIRTUALIZATION (S-IOV) ARCHITECTURE
    Publication number: 20190114283
    Abstract: Examples may include a computing platform having a host driver to get a packet descriptor of a received packet stored in a receive queue and to modify the packet descriptor from a first format to a second format. The computing platform also includes a guest virtual machine including a guest driver coupled to the host driver, the guest driver to receive the modified packet descriptor and to read a packet buffer stored in the receive queue using the modified packet descriptor, the packet buffer corresponding to the packet descriptor.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 18, 2019
    Applicants: Intel Corporation, Intel Corporation
    Inventors: Manasi DEVAL, Nrupal JANI, Anjali SINGHAI, Parthasarathy SARANGAM, Mitu AGGARWAL, Neerav PARIKH, Kiran PATIL, Rajesh M. SANKARAN, Sanjay K. KUMAR, Utkarsh Y. KAKAIYA, Philip LANTZ, Kun TIAN
  • APPARATUS AND METHOD FOR HARDWARE-ACCELERATED PACKET PROCESSING
    Publication number: 20180337850
    Abstract: Devices and techniques for hardware accelerated packet processing are described herein. A device can communicate with one or more hardware switches. The device can detect characteristics of a plurality of packet streams. The device may distribute the plurality of packet streams between the one or more hardware switches and software data plane components based on the detected characteristics of the plurality of packet streams, such that at least one packet stream is designated to be processed by the one or more hardware switches. Other embodiments are also described.
    Type: Application
    Filed: December 18, 2017
    Publication date: November 22, 2018
    Inventors: Nrupal Jani, Dinesh Kumar, Christian Maciocco, Ren Wang, Neerav Parikh, John Fastabend, Iosif Gasparakis, David J. Harriman, Patrick L. Connor, Sanjeev Jain
  • Apparatus and method for hardware-accelerated packet processing
    Patent number: 9847936
    Abstract: Devices and techniques for hardware accelerated packet processing are described herein. A device can communicate with one or more hardware switches. The device can detect characteristics of a plurality of packet streams. The device may distribute the plurality of packet streams between the one or more hardware switches and software data plane components based on the detected characteristics of the plurality of packet streams, such that at least one packet stream is designated to be processed by the one or more hardware switches. Other embodiments are also described.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: December 19, 2017
    Assignee: Intel Corporation
    Inventors: Nrupal Jani, Dinesh Kumar, Christian Maciocco, Ren Wang, Neerav Parikh, John Fastabend, Iosif Gasparakis, David J. Harriman, Patrick L. Connor, Sanjeev Jain
  • Device for indicating packet processing hints
    Patent number: 9742616
    Abstract: Devices and techniques for indicating packet processing hints are described herein. A device may receive a data packet. The device may extract a match-action attribute from the data packet that specifies an action to be applied to the data packet. The device may generate a hint field based on the match-action attribute. The hint field may include information to be used for handling the data packet. Other embodiments are also described.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: August 22, 2017
    Assignee: Intel Corporation
    Inventors: Nrupal Jani, Ilango Ganga, Daniel Daly, John Fastabend, Neerav Parikh, Elizabeth Kappler, Brian J. Skerry, Calin Gherghe, Sanjeev Jain, Ben-Zion Friedman
  • APPARATUS AND METHOD FOR HARDWARE-ACCELERATED PACKET PROCESSING
    Publication number: 20160380885
    Abstract: Devices and techniques for hardware accelerated packet processing are described herein. A device can communicate with one or more hardware switches. The device can detect characteristics of a plurality of packet streams. The device may distribute the plurality of packet streams between the one or more hardware switches and software data plane components based on the detected characteristics of the plurality of packet streams, such that at least one packet stream is designated to be processed by the one or more hardware switches. Other embodiments are also described.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 29, 2016
    Inventors: Nrupal Jani, Dinesh Kumar, Christian Maciocco, Ren Wang, Neerav Parikh, John Fastabend, Iosif Gasparakis, David J. Harriman, Patrick L. Connor, Sanjeev Jain
  • DEVICE FOR INDICATING PACKET PROCESSING HINTS
    Publication number: 20160182408
    Abstract: Devices and techniques for indicating packet processing hints are described herein. A device may receive a data packet. The device may extract a match-action attribute from the data packet that specifies an action to be applied to the data packet. The device may generate a hint field based on the match-action attribute. The hint field may include information to be used for handling the data packet. Other embodiments are also described.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 23, 2016
    Inventors: Nrupal Jani, Ilango Ganga, Daniel Daly, John Fastabend, Neerav Parikh, Elizabeth Kappler, Brian J. Skerry, Calvin Gherghe, Sanjeev Jain, Ben-Zion Friedman