Patents by Inventor Neetin Agrawal

Neetin Agrawal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reducing the effect of bulk leakage currents
    Patent number: 8203383
    Abstract: A current mirroring circuit is provided. The circuit generally comprises a current source; a first drain extended (DE) MOS transistor, a second DE MOS transistor, a current mirror, and differential amplifier. The current source is generally coupled to the current source at its drain, while the current mirror that is coupled to the sources of the first and second DE MOS transistors and to the current source. The differential amplifier generally has a first input that is coupled to the source of the first DE MOS transistor, a second input that is coupled to the source of the second DE MOS transistor, a first output that is coupled to the gate of the second DE MOS transistor, and a second output that is coupled to the gate of the first DE MOS transistor.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: June 19, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Sandeep Oswal, Neetin Agrawal
  • REDUCING THE EFFECT OF BULK LEAKAGE CURRENTS
    Publication number: 20100156389
    Abstract: A current mirroring circuit is provided. The circuit generally comprises a current source; a first drain extended (DE) MOS transistor, a second DE MOS transistor, a current mirror, and differential amplifier. The current source is generally coupled to the current source at its drain, while the current mirror that is coupled to the sources of the first and second DE MOS transistors and to the current source. The differential amplifier generally has a first input that is coupled to the source of the first DE MOS transistor, a second input that is coupled to the source of the second DE MOS transistor, a first output that is coupled to the gate of the second DE MOS transistor, and a second output that is coupled to the gate of the first DE MOS transistor.
    Type: Application
    Filed: November 23, 2009
    Publication date: June 24, 2010
    Applicant: Texas Instruments Incorporated
    Inventors: Sandeep Oswal, Neetin Agrawal