Abstract: Examples described herein relate to a cache fabric that includes a first layer of a group of routers and includes a second layer of a plurality of clusters of cache controllers. A router of the group of routers can be accessible via an interface that is to receive a memory access request from a processor and select from a group of cache controllers based on a cluster identifier and memory address and provide the memory access request to the selected group of cache controllers. The selected group of cache controllers can receive the memory access request and service a memory access request from a cache device or forward the memory access request to a second cache controller associated with the cache device or a second cache device.

Abstract: An embodiment of an integrated circuit may comprise a core, and a cache controller coupled to the core, the cache controller including circuitry to identify single re-use data evicted from a core cache, and retain the identified single re-use data in a next level cache based on an overall re-use of the next level cache. Other embodiments are disclosed and claimed.

Abstract: Systems, methods, and apparatuses relating to circuitry to implement dynamic bypassing of last level cache are described. In one embodiment, a hardware processor includes a cache to store a plurality of cache lines of data, a processing element to generate a memory request and mark the memory request with a reuse hint value, and a cache controller circuit to mark a corresponding cache line in the cache as more recently used when the memory request is a read request that is a hit in the cache and the reuse hint value is a first value, and mark the corresponding cache line in the cache as less recently used when the memory request is the read request that is the hit in the cache and the reuse hint value is a second, different value.