Abstract: A fast load current sensing apparatus and scheme provides instantaneous detection of peak current excursions using low silicon area and power efficient techniques. The response time for detecting signal excursions and measuring a signal (e.g., load current) is independent of resolution or precision and can be applied to high resolution telemetry. The apparatus sends out maximum current limit (FHC_limit) code at any instant the load current is detected to be more than a digital-to-analog converter (DAC) code. If the load current is less than the FHC_limit the scheme restores to a next DAC code as per a counter's next value. In case load current is more than FHC_limit, the scheme updates the DAC code to FHC_limit code and starts the counter from the FHC_limit.

Abstract: Techniques are described herein for automatically synthesizing programs that include one or more functions in a spreadsheet programming language. A method includes: receiving a first example including input provided in a first cell in a spreadsheet; automatically synthesizing a plurality of candidate programs including a first set of candidate programs consistent with the first example, wherein each candidate program in the first set of candidate programs comprises at least one function in a spreadsheet programming language and, when the candidate program is executed, the candidate program generates output that matches the first example; ranking the plurality of candidate programs; and storing a highest-ranked program of the plurality of candidate programs in association with the first cell in the spreadsheet.

Abstract: Techniques are described herein for automatically synthesizing programs that include one or more functions in a spreadsheet programming language. A method includes: receiving a first example including input provided in a first cell in a spreadsheet; automatically synthesizing a plurality of candidate programs including a first set of candidate programs consistent with the first example, wherein each candidate program in the first set of candidate programs comprises at least one function in a spreadsheet programming language and, when the candidate program is executed, the candidate program generates output that matches the first example; ranking the plurality of candidate programs; and storing a highest-ranked program of the plurality of candidate programs in association with the first cell in the spreadsheet.

Abstract: A fast load current sensing apparatus and scheme provides instantaneous detection of peak current excursions using low silicon area and power efficient techniques. The response time for detecting signal excursions and measuring a signal (e.g., load current) is independent of resolution or precision and can be applied to high resolution telemetry. The apparatus sends out maximum current limit (FHC_limit) code at any instant the load current is detected to be more than a digital-to-analog converter (DAC) code. If the load current is less than the FHC_limit the scheme restores to a next DAC code as per a counter's next value. In case load current is more than FHC_limit, the scheme updates the DAC code to FHC_limit code and starts the counter from the FHC_limit.

Abstract: Techniques are described herein for automatically synthesizing programs that include one or more functions in a spreadsheet programming language. A method includes: receiving a first example including input provided in a first cell in a spreadsheet; automatically synthesizing a plurality of candidate programs including a first set of candidate programs consistent with the first example, wherein each candidate program in the first set of candidate programs comprises at least one function in a spreadsheet programming language and, when the candidate program is executed, the candidate program generates output that matches the first example; ranking the plurality of candidate programs; and storing a highest-ranked program of the plurality of candidate programs in association with the first cell in the spreadsheet.

Abstract: Techniques are described herein for automatically synthesizing programs that include one or more functions in a spreadsheet programming language. A method includes: receiving first user input in a first cell in a spreadsheet; automatically synthesizing a program using the first user input in the first cell as a first example, where the program includes at least one function in a spreadsheet programming language and, when the program is executed, the program generates output that matches the first example; determining at least one additional cell in the spreadsheet that is related to the first cell; determining that a display triggering condition is satisfied; and in response to the determining that the display triggering condition is satisfied, displaying, in each of the at least one additional cell, an output of the program corresponding to the additional cell.

Abstract: Systems, methods, and non-transitory computer readable media can determine a representation of an advertisement based on a first machine learning model. The representation can be provided to a second machine learning model. One or more qualitative ratings associated with the advertisement can be determined based on the second machine learning model.

Abstract: Systems, methods, and non-transitory computer readable media can determine a representation of an advertisement based on a first machine learning model. The representation can be provided to a second machine learning model. One or more qualitative ratings associated with the advertisement can be determined based on the second machine learning model.

Abstract: A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.

Abstract: A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.

Abstract: A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.

Abstract: A built-in self-test (BIST) circuit is provided for testing an analog-to-digital converter (ADC). A multi-order sigma-delta (??) modulator has an input that receives an input signal, a first output generating analog test signal derived from the input signal and applied to an input of the ADC and a second output generating a binary data stream. A digital recombination and filtering circuit has a first input that receives the binary data stream and a second input that receives a digital test signal output from the ADC in response to the analog test signal. The digital recombination and filtering circuit combines and filters the binary data stream and digital test signal to generate a digital result signal including a signal component derived from an error introduced by operation of the ADC. A correlation circuit is used to isolate that error signal component.

Abstract: A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.

Abstract: A sigma delta analog-to-digital converter includes a sigma delta modulator including a segmented digital-to-analog converter (DAC), the segmented DAC including a coarse DAC and a fine DAC, wherein the sigma delta modulator is configured to generate a coarse quantized signal and a fine quantized signal; recombination logic configured to combine the coarse quantized signal and the fine quantized signal; and a calibration circuit, operable in a calibration mode, to calibrate the recombination logic to compensate for mismatch between the coarse DAC and the fine DAC of the segmented DAC.

Abstract: An online system or third party system allows advertisers to evaluate and test ad creatives before the ad creatives are presented to users in an ad campaign. Based on a set of test ad creatives for which feature scores and objective scores are determined by content evaluators (e.g., users, content processing algorithms), a model is trained to determine objective scores for an ad creative based on feature scores of the ad creative. The trained model is applied to a target ad creative, which has yet to be or has been presented to users, to determine one or more objective scores for the target ad creative based on feature scores of the target ad creative. Feedback is presented to an advertiser associated with the target ad creative based on the objective scores determined for the target ad creative.

Abstract: A signal processor includes one or more memory banks, wherein each memory bank stores filter coefficients; and one or more coefficient multiplexer units; each coefficient multiplexer unit being associated with a memory bank, and retrieves a filter coefficient based on a number of received input samples. The processor includes one or more multiply and accumulate (MAC) units, each MAC unit being associated with a coefficient multiplexer unit and determines a product of the retrieved filter coefficient with an input sample; retrieves a previous value stored in an associated register; computes a summation of the previous value and the product; and stores the summation in the associated register. The processor includes an output multiplexer unit to select a register, and to provide a value stored in the register as an output.

Abstract: In an embodiment, a set of input samples are filtered to provide a set of filtered samples using an N-tap filter. A steady-state-response-output sample of the N-tap filter is determined from a N/2th sample of the set of filtered samples.

Abstract: In an embodiment, a set of input samples are filtered to provide a set of filtered samples using an N-tap filter. A steady-state-response-output sample of the N-tap filter is determined from a N/2th sample of the set of filtered samples.

Abstract: A signal processor includes one or more memory banks, wherein each memory bank stores filter coefficients; and one or more coefficient multiplexer units; each coefficient multiplexer unit being associated with a memory bank, and retrieves a filter coefficient based on a number of received input samples. The processor includes one or more multiply and accumulate (MAC) units, each MAC unit being associated with a coefficient multiplexer unit and determines a product of the retrieved filter coefficient with an input sample; retrieves a previous value stored in an associated register; computes a summation of the previous value and the product; and stores the summation in the associated register. The processor includes an output multiplexer unit to select a register, and to provide a value stored in the register as an output.

Abstract: A spice packet has multiple compartments with instructions printed on a front side, where each compartment has instructions associated with a sequential step to be performed using the contents of the related compartment. The back side of the packet includes a shopping list and culinary information which may be of interest in establishing the historical background of the dish which uses the spice packet. The amounts of the spices in each packet are selected according to the strength of each individual spice which forms the contents of a packet.