Patents by Inventor Neha M. Patel
Neha M. Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11784150Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.Type: GrantFiled: May 26, 2022Date of Patent: October 10, 2023Assignee: Intel CorporationInventors: Dae-Woo Kim, Ajay Jain, Neha M. Patel, Rodrick J. Hendricks, Sujit Sharan
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Publication number: 20220285306Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.Type: ApplicationFiled: May 26, 2022Publication date: September 8, 2022Inventors: Dae-Woo KIM, Ajay JAIN, Neha M. PATEL, Rodrick J. HENDRICKS, Sujit SHARAN
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Patent number: 11380643Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.Type: GrantFiled: September 1, 2020Date of Patent: July 5, 2022Assignee: Intel CorporationInventors: Dae-Woo Kim, Ajay Jain, Neha M. Patel, Rodrick J. Hendricks, Sujit Sharan
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Publication number: 20200402940Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.Type: ApplicationFiled: September 1, 2020Publication date: December 24, 2020Inventors: Dae-Woo KIM, Ajay JAIN, Neha M. PATEL, Rodrick J. HENDRICKS, Sujit SHARAN
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Patent number: 10797014Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.Type: GrantFiled: August 16, 2016Date of Patent: October 6, 2020Assignee: Intel CorporationInventors: Dae-Woo Kim, Ajay Jain, Neha M. Patel, Rodrick J. Hendricks, Sujit Sharan
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Patent number: 10515914Abstract: Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.Type: GrantFiled: January 29, 2019Date of Patent: December 24, 2019Assignee: Intel CorporationInventors: Mihir A. Oka, Ken P. Hackenberg, Vijay Krishnan (Vijay) Subramanian, Neha M. Patel, Nachiket R. Raravikar
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Publication number: 20190157232Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.Type: ApplicationFiled: August 16, 2016Publication date: May 23, 2019Inventors: Dae-Wood Kim, Ajay Jain, Neha M. Patel, Rodrick J. Hendricks, Sujit Sharan
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Publication number: 20190157225Abstract: Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.Type: ApplicationFiled: January 29, 2019Publication date: May 23, 2019Inventors: Mihir A. OKA, Ken P. HACKENBERG, Vijay Krishnan (Vijay) SUBRAMANIAN, Neha M. PATEL, Nachiket R. RARAVIKAR
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Patent number: 10224299Abstract: Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.Type: GrantFiled: December 29, 2016Date of Patent: March 5, 2019Assignee: Intel CorporationInventors: Mihir A. Oka, Ken P. Hackenberg, Vijay Krishnan (Vijay) Subramanian, Neha M. Patel, Nachiket R. Raravikar
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Publication number: 20180190604Abstract: Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.Type: ApplicationFiled: December 29, 2016Publication date: July 5, 2018Inventors: Mihir A. OKA, Ken P. HACKENBERG, Vijay Krishnan (Vijay) SUBRAMANIAN, Neha M. PATEL, Nachiket R. RARAVIKAR
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Publication number: 20140013855Abstract: A deflection sensor is disclosed herein. The deflection sensor includes a nanotube film adjacent to a substrate, and first and second contacts electrically connectable with the nanotube film. Methods of making and using the deflection sensor are also disclosed.Type: ApplicationFiled: September 19, 2013Publication date: January 16, 2014Inventors: Mohammad M. FARAHANI, Vladimir Noveski, Neha M. Patel, Nachiket R. Raravikar
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Patent number: 8586393Abstract: A stress sensor is disclosed herein. The stress sensor includes a plurality of carbon nanotubes in a substrate, and first and second contacts electrically connectable with the plurality of carbon nanotubes. Methods of making and using the stress sensor are also disclosed.Type: GrantFiled: April 11, 2012Date of Patent: November 19, 2013Assignee: Intel CorporationInventors: Mohammad M. Farahani, Vladimir Noveski, Neha M. Patel, Nachiket R. Raravikar
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Publication number: 20120193734Abstract: A stress sensor is disclosed herein. The stress sensor includes a plurality of carbon nanotubes in a substrate, and first and second contacts electrically connectable with the plurality of carbon nanotubes. Methods of making and using the stress sensor are also disclosed.Type: ApplicationFiled: April 11, 2012Publication date: August 2, 2012Applicant: Intel CorporationInventors: Mohammad M. Farahani, Vladimir Noveski, Neha M. Patel, Nachiket R. Raravikar
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Patent number: 8174084Abstract: A stress sensor is disclosed herein. The stress sensor includes a plurality of carbon nanotubes in a substrate, and first and second contacts electrically connectable with the plurality of carbon nanotubes. Methods of making and using the stress sensor are also disclosed.Type: GrantFiled: September 19, 2006Date of Patent: May 8, 2012Assignee: Intel CorporationInventors: Mohammad M. Farahani, Vladimir Noveski, Neha M. Patel, Nachiket R. Raravikar
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Patent number: 7553681Abstract: An embodiment of the present invention is a technique to form stress sensors on a package in situ. A first array of carbon nanotubes (CNTs) aligned in a first orientation is deposited at a first location on a substrate or a die in a wafer. The first array is intercalated with polymer. The first polymer-intercalated array is covered with a protective layer. A second array of CNTs aligned in a second orientation is deposited at a second location on the substrate or the die. The second array is intercalated with polymer.Type: GrantFiled: March 24, 2006Date of Patent: June 30, 2009Assignee: Intel CorporationInventors: Nachiket R. Raravikar, Neha M. Patel
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Publication number: 20080067619Abstract: A stress sensor is disclosed herein. The stress sensor includes a plurality of carbon nanotubes in a substrate, and first and second contacts electrically connectable with the plurality of carbon nanotubes. Methods of making and using the stress sensor are also disclosed.Type: ApplicationFiled: September 19, 2006Publication date: March 20, 2008Inventors: Mohammad M. Farahani, Vladimir Noveski, Neha M. Patel, Nachiket R. Raravikar