Patents by Inventor Neha Nayyar
Neha Nayyar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230395675Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cross couple design for high density standard cells and methods of manufacture. The structure includes a first contact connected in a cross couple circuit to at least two gate structures, and a second contact connected to the first contact at a location which is devoid of any via connection.Type: ApplicationFiled: June 7, 2022Publication date: December 7, 2023Inventors: James P. MAZZA, Jia ZENG, Xuelian ZHU, Mahbub RASHED, Neha NAYYAR, Collin A. TRANTER
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Publication number: 20230147981Abstract: A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.Type: ApplicationFiled: January 3, 2023Publication date: May 11, 2023Inventors: David Pritchard, Heng Yang, Hongru Ren, Neha Nayyar, Manjunatha Prabhu, Elizabeth Strehlow, Salvatore Cimino
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Patent number: 11581430Abstract: A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.Type: GrantFiled: August 22, 2019Date of Patent: February 14, 2023Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: David Pritchard, Heng Yang, Hongru Ren, Neha Nayyar, Manjunatha Prabhu, Elizabeth Strehlow, Salvatore Cimino
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Patent number: 11239087Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.Type: GrantFiled: October 24, 2019Date of Patent: February 1, 2022Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Heng Yang, David C. Pritchard, George J. Kluth, Anurag Mittal, Hongru Ren, Manjunatha G. Prabhu, Kai Sun, Neha Nayyar, Lixia Lei
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Patent number: 11177182Abstract: One illustrative vertical transistor device disclosed herein includes a channel region comprising at least one layer of a two-dimensional (2D) material, a bottom source/drain region, a top source/drain region and a gate structure positioned all around at least the at least one layer of a two-dimensional (2D) material.Type: GrantFiled: January 30, 2020Date of Patent: November 16, 2021Assignee: GlobalFoundries U.S. Inc.Inventors: Heng Yang, David Pritchard, Kai Sun, Hongru Ren, Neha Nayyar, Manjunatha Prabhu, Elizabeth Strehlow, Salvatore Cimino
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Patent number: 11094791Abstract: One illustrative device disclosed herein includes a bottom source/drain region and a top source/drain region positioned vertically above at least a portion of the bottom source/drain region, wherein each of the bottom source/drain region and the top source/drain region comprise at least one layer of a two-dimensional (2D) material. The device also includes a substantially vertically oriented semiconductor structure positioned vertically between the bottom source/drain region and the top source/drain region and a gate structure positioned all around an outer perimeter of the substantially vertically oriented semiconductor structure for at least a portion of the vertical height of the substantially vertically oriented semiconductor structure.Type: GrantFiled: January 30, 2020Date of Patent: August 17, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Heng Yang, David Pritchard, Kai Sun, Hongru Ren, Neha Nayyar, Manjunatha Prabhu, Elizabeth Strehlow, Salvatore Cimino
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Publication number: 20210242094Abstract: One illustrative vertical transistor device disclosed herein includes a channel region comprising at least one layer of a two-dimensional (2D) material, a bottom source/drain region, a top source/drain region and a gate structure positioned all around at least the at least one layer of a two-dimensional (2D) material.Type: ApplicationFiled: January 30, 2020Publication date: August 5, 2021Inventors: Heng Yang, David Pritchard, Kai Sun, Hongru Ren, Neha Nayyar, Manjunatha Prabhu, Elizabeth Strehlow, Salvatore Cimino
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Publication number: 20210242316Abstract: One illustrative device disclosed herein includes a bottom source/drain region and a top source/drain region positioned vertically above at least a portion of the bottom source/drain region, wherein each of the bottom source/drain region and the top source/drain region comprise at least one layer of a two-dimensional (2D) material. The device also includes a substantially vertically oriented semiconductor structure positioned vertically between the bottom source/drain region and the top source/drain region and a gate structure positioned all around an outer perimeter of the substantially vertically oriented semiconductor structure for at least a portion of the vertical height of the substantially vertically oriented semiconductor structure.Type: ApplicationFiled: January 30, 2020Publication date: August 5, 2021Inventors: Heng Yang, David Pritchard, Kai Sun, Hongru Ren, Neha Nayyar, Manjunatha Prabhu, Elizabeth Strehlow, Salvatore Cimino
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Publication number: 20210057558Abstract: A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.Type: ApplicationFiled: August 22, 2019Publication date: February 25, 2021Inventors: David Pritchard, Heng Yang, Hongru Ren, Neha Nayyar, Manjunatha Prabhu, Elizabeth Strehlow, Salvatore Cimino
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Patent number: 10691862Abstract: The present disclosure relates to methodologies for designing semiconductor structures, and, more particularly, creating a methodology to connect contacts of semiconductor elements to a metal line using marker tabs to reserve space for future connections between the contacts and the metal line, and then reassigning the marker tabs to connections between the contacts and the metal line on different levels of a metal stack formed over the semiconductor elements.Type: GrantFiled: July 7, 2017Date of Patent: June 23, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Neha Nayyar, Daniel J. Dechene, David C. Pritchard, George J. Kluth
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Publication number: 20200058515Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.Type: ApplicationFiled: October 24, 2019Publication date: February 20, 2020Inventors: Heng YANG, David C. PRITCHARD, George J. KLUTH, Anurag MITTAL, Hongru REN, Manjunatha G. PRABHU, Kai SUN, Neha NAYYAR, Lixia LEI
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Patent number: 10566384Abstract: Methods of fabricating a flexible dummy fill to increase MTJ density are provided. Embodiments include forming a first oxide layer; forming lower interconnect layers in the first oxide layer; forming a nitride layer over the first oxide layer and the lower interconnect layers; forming a second oxide layer over the nitride layer; forming bottom electrodes through the second oxide layer and the nitride layer contacting a portion of an upper surface of the lower interconnect layers; forming MTJ structures over the bottom electrodes; forming top electrodes over the MTJ structures; and forming upper interconnect layers over one or more of the top electrodes.Type: GrantFiled: October 30, 2018Date of Patent: February 18, 2020Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Wanbing Yi, Neha Nayyar, Curtis Chun-I Hsieh, Mahesh Bhatkar, Wenjun Liu, Juan Boon Tan
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Patent number: 10497576Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.Type: GrantFiled: August 20, 2018Date of Patent: December 3, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Heng Yang, David C. Pritchard, George J. Kluth, Anurag Mittal, Hongru Ren, Manjunatha G. Prabhu, Kai Sun, Neha Nayyar, Lixia Lei
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Publication number: 20190074434Abstract: Methods of fabricating a flexible dummy fill to increase MTJ density are provided. Embodiments include forming a first oxide layer; forming lower interconnect layers in the first oxide layer; forming a nitride layer over the first oxide layer and the lower interconnect layers; forming a second oxide layer over the nitride layer; forming bottom electrodes through the second oxide layer and the nitride layer contacting a portion of an upper surface of the lower interconnect layers; forming MTJ structures over the bottom electrodes; forming top electrodes over the MTJ structures; and forming upper interconnect layers over one or more of the top electrodes.Type: ApplicationFiled: October 30, 2018Publication date: March 7, 2019Inventors: Wanbing YI, Neha NAYYAR, Curtis Chun-I HSIEH, Mahesh BHATKAR, Wenjun LIU, Juan Boon TAN
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Patent number: 10186524Abstract: Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.Type: GrantFiled: March 5, 2018Date of Patent: January 22, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: David Pritchard, Lixia Lei, Deniz E. Civay, Scott D. Luning, Neha Nayyar
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Publication number: 20190012422Abstract: The present disclosure relates to methodologies for designing semiconductor structures, and, more particularly, creating a methodology to connect contacts of semiconductor elements to a metal line using marker tabs to reserve space for future connections between the contacts and the metal line, and then reassigning the marker tabs to connections between the contacts and the metal line on different levels of a metal stack formed over the semiconductor elements.Type: ApplicationFiled: July 7, 2017Publication date: January 10, 2019Inventors: Neha NAYYAR, Daniel J. DECHENE, David C. PRITCHARD, George J. KLUTH
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Patent number: 10158066Abstract: Methods of fabricating a flexible dummy fill to increase MTJ density are provided. Embodiments include forming a first oxide layer; forming lower interconnect layers in the first oxide layer; forming a nitride layer over the first oxide layer and the lower interconnect layers; forming a second oxide layer over the nitride layer; forming bottom electrodes through the second oxide layer and the nitride layer contacting a portion of an upper surface of the lower interconnect layers; forming MTJ structures over the bottom electrodes; forming top electrodes over the MTJ structures; and forming upper interconnect layers over one or more of the top electrodes.Type: GrantFiled: June 7, 2017Date of Patent: December 18, 2018Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Wanbing Yi, Neha Nayyar, Curtis Chun-I Hsieh, Mahesh Bhatkar, Wenjun Liu, Juan Boon Tan
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Publication number: 20180358546Abstract: Methods of fabricating a flexible dummy fill to increase MTJ density are provided. Embodiments include forming a first oxide layer; forming lower interconnect layers in the first oxide layer; forming a nitride layer over the first oxide layer and the lower interconnect layers; forming a second oxide layer over the nitride layer; forming bottom electrodes through the second oxide layer and the nitride layer contacting a portion of an upper surface of the lower interconnect layers; forming MTJ structures over the bottom electrodes; forming top electrodes over the MTJ structures; and forming upper interconnect layers over one or more of the top electrodes.Type: ApplicationFiled: June 7, 2017Publication date: December 13, 2018Inventors: Wanbing YI, Neha NAYYAR, Curtis Chun-I HSIEH, Mahesh BHATKAR, Wenjun LIU, Juan Boon TAN
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Publication number: 20180197882Abstract: Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.Type: ApplicationFiled: March 5, 2018Publication date: July 12, 2018Inventors: David PRITCHARD, Lixia LEI, Deniz E. CIVAY, Scott D. LUNING, Neha NAYYAR
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Patent number: 9941301Abstract: Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.Type: GrantFiled: December 22, 2016Date of Patent: April 10, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: David Pritchard, Lixia Lei, Deniz E. Civay, Scott D. Luning, Neha Nayyar