Abstract: The invention relates to a microprocessor device and to a branch prediction method that determines which of a plurality of predetermined branch classes a respective branch instruction to be executed is assigned to, and determines whether the branch is likely to be taken or not, depending on the branch class determined. Advantageously, a respective adaptive branch prediction device assigned to the determined branch class is used for determining whether the branch is likely to be taken or not.

Abstract: A variable length instruction pipeline includes optional expansion stages that can be included in the variable length instruction pipeline to avoid pipeline stalls. The expansion stages are removed from the variable length instruction pipeline when not needed to reduce the length of the pipeline, which reduces latency and other problems associated with long pipelines. For example, in one embodiment of the present invention, a variable length instruction pipeline includes a first pipeline stage, a first expansion stage, and a second pipeline stage. The second pipeline stage is configured to selectively receive instructions from the first pipeline stage or the first expansion stage if the first expansion stage holds an instruction.

Abstract: A data management system is disclosed that includes a database and one or more interfaces to allow access the database. The database stores data such as data describing a product. Vendors, such as manufacturers and representatives of the manufacturers, view and are able to enter and maintain the product information data. Buyers, such as wholesalers, distributors and retailers, may utilize the data in the database to provide information to customers about the products it sells. To provide the customers with the information, the data may be used to create catalogs or to provide the product information on-line, such as through the Internet.

Abstract: In a contents addressable memory for a fully associative cache memory in which address bit values in respect of data to be retrieved from cache are applied to the bit lines of respective columns of cells for comparison with the bit values held by the cells, a match in any one cell is arranged to forward bias a match line device in that cell, the match line devices of a row being connected in cascade, so that if a match is obtained along a row a current path is provided along the row to a respective current sensing circuit to indicate the match.