Abstract: An apparatus has a cache configured to store entries which correspond to blocks of addresses having one of a plurality of sizes as selected by a control device. When the control device has not yet indicated which size to use, cache access circuitry assumes a default size which is greater than at least one of the plurality of sizes.

Abstract: An apparatus has a cache configured to store entries which correspond to blocks of addresses having one of a plurality of sizes as selected by a control device. When the control device has not yet indicated which size to use, cache access circuitry assumes a default size which is greater than at least one of the plurality of sizes.

Abstract: The present invention provides a memory controller and memory controlling method for controlling transfers to or from a memory device of a type where each transfer comprises a sequence of distinct phases and the actual sequence of distinct phases is dependent on the type of transfer. In a particularly preferred embodiment, the memory device is a NAND flash memory device. The memory controller comprises a memory device interface operable to couple the memory controller with the memory device, a number of programmable timing registers programmable to store timing information appropriate for the memory device whose transfers are to be controlled by the memory controller, and a number of programmable control registers which, prior to each transfer, are programmable to define the actual sequence of distinct phases to be performed for that transfer and one or more control values for that transfer.