Abstract: A power system includes a battery back-up unit (BBU) having back-up battery circuitry which provides battery back-up support for a plurality of power supplies each having a respective power factor correction circuit front-end with a boost stage. The voltages output from the boost stages of the power supplies are monitored and compared with respective reference threshold voltages to derive a signal which is used to bring battery back-up power on-line when a monitored voltage falls below a threshold voltage, which may be indicative of a loss of AC mains input voltage. AC mains input voltage is also monitored to detect a restoration and disconnect the battery back-up power. In the event that battery back-up is brought on-line due to a faulty power supply rather than a loss of AC mains input voltage, the faulty power supply can be masked and reported for repair.

Abstract: A battery capacity test and electronic system implementing the same tests both the high and low discharge capacities of a back-up battery to ensure that the battery is capable of handling both a short term, high discharge load and a long term, low discharge load. The battery capacity test is particularly suitable for use in an electronic system which, upon occurrence of a power outage, converts from an operational mode to a power saving mode during a conversion time. High discharge capacity testing is performed using a "safety net" where the primary power source of the electronic system is switched to a reduced testing voltage output, rather than shut off or disconnected, so that the primary power source can take over quickly in the event of a back-up power supply failure during the test.

Abstract: A plurality of nodes in a network are connected in a tree arrangement. A master control node is at the root of the tree. Each connection between a parent node and a child node in the tree consists of only one pair of wires, over which data bits are transmitted serially. To avoid contention, communications are always initiated by the parent node. The child node detects the end of message when no more data is received for a set timeout period. The child node then has a specified time interval for response to the communication, during which interval it has control of the line. After the end of the interval, control reverts to the parent. If a message has been received from the child within that time, normal status is resumed; oterwise, the parent retries the message or takes other error recovery actions. In the preferred embodiment, the network is used to monitor power conditions at a plurality of nodes in a computer system.

Abstract: An automatic address assignment system has a plurality of I/O devices coupled to a bus. Each device contains a unique machine-readable identifier which is used to select the device for address assignment. The identifier is a binary bit string. Each bit position in the bit string is selected by the host in a serial manner with the host specifying which binary value is being solicited. All devices whose identifier digit matches the solicited value respond positively and remain in contention for address assignment. The other devices will not respond and drop out of contention for address assignment until the sequence is restarted from the first bit. After the bit sequence is completed, the address for that device is bused to the device, and the sequence is restarted from the first bit until all devices have been assigned an address.

Abstract: A system for controlling the cycle time of a central processing unit having associated control store memory units for the storage of information is provided. The system includes a plurality of control store memory locations disposed within the control store memory units for the storage of information. A plurality of control store memory locations are operable at varying speeds and are accessible by the central processing unit. Circuitry is provided for addressing one of the plurality of control store memory locations responsive to address information contained within the information stored within the plurality of control store memory locations. The addressed information selects the next successive control store memory location to be addressed by a central processing unit.

Abstract: A high density CMOS dynamic RAM cell comprising a transistor and capacitance means formed in an n-well is disclosed. The capacitance means includes a polysilicon plate member disposed above a p-type region formed in the n-well. A buried contact, extending from the plate member, pierces the p-type region and contacts the well. In addition to the capacitance associated with the plate member, p-type region and well, capacitance is obtained between the side walls of the n-type regions and p-type regions.

Abstract: A digital computer system including a computation unit (14), a main store (12), a virtual address translator (10), a microinstruction control unit (170) and an instruction code prefetch circuit (212). User instruction codes are stored sequentially in the main store (12) which is accessed for read and write operations by the virtual address translator (10). The instruction code prefetch circuit (212) retrieves the user instruction codes from the main store (12) and holds the instruction codes in a register (16, 18). The instruction codes are transferred from the register (16, 18) to the computation unit (14) in sequential order of use. The microinstruction control unit (170) produces selected microinstructions which are executed by the computation unit (14) to accomplish the operations specified by the user instructions. Designated microinstructions include commands which activate the instruction code prefetch circuit (212) to retrieve the succeeding user instruction codes from the main store (12).

Abstract: A maintenance interface is provided for interfacing a service processor and a central processing unit operating asynchronously to each other. The maintenance interface includes circuitry for synchronizing the service processor to the central processing unit and decode circuitry for interpreting commands from the service processor. The maintenance interface also includes circuitry responsive to control signals from the central processing unit such that the maintenance interface establishes communication between the service processor and the central processing unit. The central processing unit includes a microprocessor for interpreting data sent between the service processor and the central processing unit. The maintenance interface is responsive to control signals from the central processing unit to resolve communication contention between the central processing unit and the service processor.

Abstract: Control circuitry is provided for controlling the generation of a block check word simultaneously with the writing of control words into a transient area of a writeable control storage. The control circuitry in response to a write control storage instruction generates control signals for controlling existing central processing unit (CPU) hardware to effect generation of the block check word while a control word is being written into the transient area of control storage. Microinstructions in the resident area for performing the overlay force selection of a local storage register which has been initialized. The operand from the local storage register is applied to the ALU together with the word which is also being written into control storage. The ALU is forced to perform an exclusive OR operation and the result is returned to the selected LSR. In this manner a block check word is dynamically calculated word by word as each word is written into control storage.

Abstract: A control system for a computer includes a control store (30) for storing end op, I-1, I-2 and return words. A microinstruction decode and control unit (170) responds to end op words to initialize and personalize computer components to facilitate subsequent execution of a high level instruction. The control unit (170), in conjunction with a next address logic (162), selects the next microinstruction to be executed in response to a high level instruction. The control unit (170) and logic (162) are responsive to I-1 words to personalize the computer and to select a microinstruction to begin E-phase of a high level instruction. In response to I-2 control words, the control unit (170) and logic (162) select an operand fetch routine in the control store (30), and write a first E-phase address into a local store (138). The return word gates the first E-phase address from the local store (138) to select a microinstruction in the control store (3) to being E-phase.

Abstract: Improved efficiency in the operation of a computer system is achieved by interface logic that controls the operating rate of a central processing unit to be compatible with the slower operating rate of main memory. Microinstructions are decoded and interlock latches are generated to provide a main store interface holdoff signal that is applied to holdoff latch logic. Normally, the holdoff latch logic provides load control signals to sequence the operating cycle of the central processing unit. Under certain identified microinstruction conditions, an interlock latch is generated and the load control signals are not output from the holdoff logic, thereby inhibiting the sequencing operation of the central processing unit. Interlock latches that are generated include a register-in-use interlock and an invalid data interlock for each register that is used to fetch data from and store data into main memory.