Abstract: A light pen input system includes a light sensing device (10) having a row and column array of light sensing elements (14) over which a light pen (12) is moved to write in information, e.g. for display on a display screen, the light beam emitted by the pen producing a light spot (20) on the array which covers, and is sensed by, adjacent elements and which, with the beam directed perpendicularly to the array, is substantially non-circular in shape, having dimensions in two directions over the array which differ from one another. Rotation of the pen around its axis is then detectable, providing additional functionality. An elongated light spot, e.g. elliptical, rectangular or triangular, provides further capabilities in enabling the width of a written stroke to be varied by twisting the pen.

Abstract: An image sensor comprises an image capturing device 10 and a lens arrangement 20, 30, 40, positioned between an area to be imaged and the image capturing device 10. The lens arrangement includes at least one array 40 of spaced lens elements 42 for transmitting light from a portion of the area to be imaged to a portion of the device 10. Light emitting apparatus 46, for example electroluminescent strips, are disposed in or over the spacing between the lens elements 42. This provides a compact optical focusing and illumination system. A color imaging system may be provided using discrete colored light sources.

Abstract: A charge measurement circuit 20 includes a charge sensitive amplifier 40 which holds the input 42 at a constant voltage. A compensation circuit 72, 74, 76, 80 enables a current to be supplied to or drained from a charge supplying circuit 32. This current is selected such that any voltage mismatch between the output of the supplying circuit 32 and the input 42 of the measurement circuit 20 does not result in a charge flow which causes errors in the measured signal.

Abstract: An array of electrical elements is arranged in rows and columns, signals being read out from the column conductors. Each column has a multiplexer switch so that signals from a number of columns may be switched to a common output. Each multiplexer switch comprises a diode bridge (36-39) having an input (60) and an output (34). Current is supplied to the diode bridge through a supply diode (52) and drained from the bridge through a drain diode (54), for controlling the switching of the bridge. The all-diode switch may be integrated on the substrate of the array and has a substantially linear switching response.

Abstract: A large-area electronic device comprises an array (1) of device elements (2,3) coupled to row and column conductors (A and B). The column conductors (B) are arranged in groups, (e.g M, M+1, M+2), and a column multiplexer circuit (C) couples the column conductors (B) of a respective group to a respective common terminal (5). The present invention provides a compatible multiplexer circuit (C) for the array (1), the operation of the circuit (C) using electrical switching rather than optical switching. This multiplexer circuit (C) for each column conductor comprises a diode bridge (SD3 to SD6) and may include a clamping switch (SD1, SD2). A signal is transmitted between the column conductor (B) and a common output terminal (5) in a first state of the diode bridge (SD3 to SD6). The potential of the column conductor (B) is clamped by the clamping switch (SD1, SD2) in a second state of the diode bridge.

Abstract: Audio signal reproduction apparatus, for example, an in-car entertainment system, includes a number of audio signal sources (I--I to I-N) which are selected by means of a selector (2) and fed to an AGC circuit (4) before being applied to an amplifier (6) and loudspeaker (7). The AGC circuit (4) includes an amplitude analyzer (42) and a low-pass filter (43) to produce an output signal (44) which controls the gain of an amplifier (41). The arrangement is such that the AGC circuit only causes a gain change when the audio signal lies outside a predetermined amplitude band for a given minimum time period. Thus only long "too loud" or "too soft" passages cause a gain change and transients pass through the arrangement without causing a gain change.

Abstract: A flat panel display, image sensor memory device, or other type of large area electronic device, particularly but not exclusively with thin-film circuitry, includes an array of device elements (8) which are arranged in rows (N . . . ) and columns (M . . . ) with the device elements (8) in each pair of neighbouring columns (M, M+1) sharing a column conductor (11). The device elements (8) are coupled to their associated row conductor (21) via a first switching element (S1). In each pair (M, M+1) of neighbouring columns, the device elements (8) share a column conductor (11). Each device element of a row (n) in one column (M) of each pair is coupled via a respective second switching element (S2) to one reference conductor (1), while each device element (8) of the same row (N) in the other column (M+1) of the pair is coupled via a respective second switching element (S2) to another reference conductor (2).

Abstract: Each imaging element (2a) of an array (2) includes a photosensitive element (3) for sensing light incident on the imaging element (2a) and for storing charge representing the incident light and a rectifying element (D1). The imaging elements (2a) are arranged in rows and columns with each photosensitive element (3) and the associated rectifying element (D1) being coupled in series between an associated first conductor (4) and an associated second conductor (5, 6) for allowing charge stored at a selected imaging element (2a) to be read out by applying voltages to the second conductors (5, 6) to forward bias the rectifying element (D1) of the selected imaging element to cause a current representing the charge stored at the photosensitive element (3) of the selected imaging (2a) element to flow through the associated first conductor (4).

Abstract: The charge storage elements (3) of an array (2) are arranged in columns and rows and each column is coupled to an associated column conductor (4). Each storage element (3) in a row is coupled to an associated second conductor by a first rectifying element (D1) and to an associated third conductor by a second rectifying element (D2). Each row shares its second and third conductors (5a, 5b, 6a, 6b) with any adjacent rows. One of the two conductors of each row forms a row conductor (5a, 5b) and the other (6a, 6b) one of first and second reference conductors (6a and 6b). Adjacent row conductors (5a, 5b) are separated by a reference conductor (6a or 6b). Each first reference conductor (6a) is separated from any other first reference conductor (6a) by two row conductors (5a, 5b) and a second reference conductor (6b).

Abstract: The storage elements (3) of an array (2) are arranged in rows and columns with the storage elements (3) in a column being coupled to a first conductor (4) and the storage elements (3) in a row being coupled to a second (5) and to a third (6) conductor. Each storage element (3) in a row is coupled to the associated second conductor (5) by a first rectifying element (D1) and to the associated third conductor (6) by a second rectifying element (D2) with the first and second rectifying elements (D1 and D2) allowing the passage of current when forward-biased by applied voltages. The third conductors (6) also form the second conductors (5) of any adjacent rows. The first and second rectifying elements (D1' and D2') of alternate rows (N, N+2, N+4, . . . ) are oppositely oriented to those (D1" and D2") in the remaining rows (N+1, N+3, . . . ).

Abstract: A first substrate (2) carries an electro-optic display (3) having a first array (4) of display elements (5) and conductors (12,13) for addressing individual display elements (5) to enable the display to display an image. A second substrate (6) carries a second array (7) of elements (8) addressable by conductors (9,10). Photosensitive elements (11) are associated with the conductors (9,10) for supplying, when illuminated, signals along the conductors (9,10) for accessing the elements (8) of the second array (7), the second substrate (6) being provided over the first substrate (2) so that the photosensitive elements (11) are associated with selected ones (5') of the display elements (5) for enabling the selected display elements (5a) to illuminate the photosensitive elements (11) allowing access of the elements (8) of the second array (7) to be controlled by the display (3) so that it is not necessary to provide separate drive circuitry for the second array.

Abstract: A two-dimensional array (2) of imaging elements (3) is arranged in rows and columns. Each imaging element (3) has a two terminal component (40) for sensing light incident on the imaging element and for storing charge representing the incident light. A plurality of row and column conductors (5 and 6) are provided with one of the two terminals (4a,4b) of each component (40) in a row being coupled to the associated row conductor (5) and the other one of the two terminals (4a,4b) to the associated column conductor (6). Voltage signals are applied to the row and column conductors (5 and 6) for enabling the components (40) to sense light incident on the array (2) and to enable charge stored at a selected imaging element (3) to be sensed. The rows of imaging elements (3) are arranged in first and second sets (S1 and S2). A voltage signal of one polarity is applied to a row conductor (5) associated with the first set (S1) to enable charge stored at an imaging element (3) in the associated row (5) to be sensed.

Abstract: A semiconductor memory device includes an array of rows and columns of field effect transistors (FETs) which provide memory locations. The FET gate electrodes in each row are connected to a respective row conductor and the FET first and second main electrodes in each column are connected to respective adjacent column conductors so that the second main electrodes in one column are connected to the first electrodes of the FETs in any adjacent column. Circuitry is provided for storing data at and reading data from the memory locations. The circuitry stores data at a desired memory location by applying a first predetermined voltage V.sub.g.sup.W to a selected row conductor and a second predetermined voltage V.sub.d.sup.

Abstract: An electronic matrix array device such as a data store, e.g. a datacard, or an electro-optic active matrix display, has crossing sets of row and column conductors and matrix elements such as memory or picture cells at the crossing intersections. At least some of the matrix elements include a two-terminal thin film non-linear impedance element which may be bi-directional, such as a MIM, or unidirectional, such as a diode. The array device also includes a row address decoder for addressing the row conductors and a column address decoder for addressing the column conductors, either or both decoders having respective stages for respective conductors of the relevant set of conductors.

Abstract: In an opto-electronic memory system having a memory element (14), for example an optical data card, in which optically-encoded data is stored in rows of memory locations (17) and reading elements (10,12) comprising a photosensitive element array (12) and operable to read out stored data in response to illumination of the memory locations, data is stored at memory locations as colors representing different data values and the memory locations are addressed with reading light of different colors in sequence, thereby enabling higher data storage capacities to be obtained. The memory locations may be reflective or transmissive. The reading elements may comprise linear or two dimensional arrays of photosensitive elements.

Abstract: A combined matrix display and light sensing device comprising arrays of display elements (12) and light sensing elements (18) connected to a first set of address conductors (14) to which scan signals (15) are applied, a second set of address conductors (16) through which data signals from a drive circuit (30) are supplied to the display elements (12) and to which a detection circuit (40) is connected to detect illumination of sensing elements. The detection circuit comprises charge sensitive amplifier circuits (45) which serve also as buffer amplifiers for data signals from the drive circuit (30). Each circuit (45) comprises an output, a first input connected to a conductor of the second set, a second input, and a switch (48) and capacitor (47) connected in parallel between the output and the first input.

Abstract: The image sensor (1a) has a transparent substrate (2) supporting a two dimensional array (3) of photosensitive and switching elements (4) with switching signal conductors (5) and data signal conductors (6) connected to the photosensitive and switching elements (4) for enabling individual photosensitive elements to be accessed. The photosensitive and switching elements (4) and the conductors (5 and 6) are arranged such that at least half of the area of the image sensor is transparent during operation. Each photosensitive element is electrically coupled to a respective capacitor (7) for storing charge generated as a result of light being incident on the photosensitive element. The capacitors (7) are formed so as to be transparent and so as to occupy a significant part of the entire area of the array (3).

Abstract: An analogue current memory has a current input (1) which is connected to the input branch of a first current mirror circuit formed by two transistors (T4 and T8). The input and output branches of the first current mirror are isolated by a first switch (S1) which is controlled by a clock signal .phi.A. The output branch of the first current mirror is connected to the input branch of a second current mirror formed by two transistors (T9 and T12). The input and output branches of the second current mirror are isolated by a second switch (S2) which is controlled by a clock signal .phi.B which does not overlap the clock signal .phi.A. The first switch is closed during the first half of the sample period and the second switch is closed during the second half. A current fed to input 1 is mirrored by the transistor T8 while the first switch (S1) is closed and a first capacitor (CA) charges to the gate/source voltage of transistor T8.

Abstract: A sampled analog electrical signal in the form of sample currents is processed by combining the input sample current in one sample period with sample currents derived from input sample currents in preceding sample periods. The signal processing is performed by scaling, adding, subtracting and storing sample currents. A circuit arrangement for carrying out the signal processing may be constructed from current mirror circuits and a current memory which is capable of reproducing at its output in one sample period the current applied to its input in a previous sample period.