Patents by Inventor Neil Deutscher
Neil Deutscher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10879922Abstract: An analog to digital converter (ADC) includes voltage inputs, a transconductor configured to convert the voltage inputs into currents, current-controlled oscillators, a counter, and digital logic. The current-controlled oscillators propagate respect currents from the transconductor. The counter is configured to count repeated traversal of one or more oscillators. The digital logic is configured to, based upon results from the counter, provide a code configured to indicate a value of associated voltage input.Type: GrantFiled: August 7, 2019Date of Patent: December 29, 2020Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Neil Deutscher, Bryan Kris
-
Publication number: 20200059239Abstract: An analog to digital converter (ADC) includes voltage inputs, a transconductor configured to convert the voltage inputs into currents, current-controlled oscillators, a counter, and digital logic. The current-controlled oscillators propagate respect currents from the transconductor. The counter is configured to count repeated traversal of one or more oscillators. The digital logic is configured to, based upon results from the counter, provide a code configured to indicate a value of associated voltage input.Type: ApplicationFiled: August 7, 2019Publication date: February 20, 2020Applicant: Microchip Technology IncorporatedInventors: Neil Deutscher, Bryan Kris
-
Patent number: 10171099Abstract: A differential digital delay line analog-to-digital converter (ADC) includes differential digital delay lines, a circuit including a set of delay elements included in the differential digital delay lines, and another circuit including another set of delay elements included in the differential digital delay lines. The first circuit is configured to generate data representing an analog to digital conversion of an input. The second circuit is configured to calibrate a source to the differential digital delay lines.Type: GrantFiled: April 10, 2018Date of Patent: January 1, 2019Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Bryan Kris, Neil Deutscher
-
Patent number: 10122375Abstract: Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC), comprising differential digital delay lines including series coupled delay cells, wherein a delay time of a first delay line is controlled by a first input of the ADC and a delay time of a second delay line is controlled by a second input of the ADC. The ADC includes a pair of bypass multiplexers coupled at a predefined node location in the series coupled delay cells, latches each coupled with the series coupled delay cells, a converter circuit coupled with the plurality of latches configured to convert data from the latches into an output value of the ADC, and logic circuits configured to select data from the series coupled delay cells to the latches depending on a selected resolution of the differential digital delay line analog-to-digital converter.Type: GrantFiled: March 8, 2018Date of Patent: November 6, 2018Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Bryan Kris, Neil Deutscher, Thomas S. Spohrer
-
Patent number: 10090850Abstract: Embodiments of the present disclosure include a microcontroller with a processor, memory, and peripheral devices including a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines, a circuit including a set of delay elements included in the differential digital delay lines, and another circuit including another set of delay elements included in the differential digital delay lines. The first circuit is configured to generate data representing an analog to digital conversion of an input. The second circuit is configured to calibrate a source to the differential digital delay lines.Type: GrantFiled: April 11, 2017Date of Patent: October 2, 2018Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Bryan Kris, Neil Deutscher
-
Publication number: 20180226984Abstract: Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines, a circuit including a set of delay elements included in the differential digital delay lines, and another circuit including another set of delay elements included in the differential digital delay lines. The first circuit is configured to generate data representing an analog to digital conversion of an input. The second circuit is configured to calibrate a source to the differential digital delay lines.Type: ApplicationFiled: April 10, 2018Publication date: August 9, 2018Applicant: Microchip Technology IncorporatedInventors: Bryan Kris, Neil Deutscher
-
Publication number: 20180198461Abstract: Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC), comprising differential digital delay lines including series coupled delay cells, wherein a delay time of a first delay line is controlled by a first input of the ADC and a delay time of a second delay line is controlled by a second input of the ADC. The ADC includes a pair of bypass multiplexers coupled at a predefined node location in the series coupled delay cells, latches each coupled with the series coupled delay cells, a converter circuit coupled with the plurality of latches configured to convert data from the latches into an output value of the ADC, and logic circuits configured to select data from the series coupled delay cells to the latches depending on a selected resolution of the differential digital delay line analog-to-digital converter.Type: ApplicationFiled: March 8, 2018Publication date: July 12, 2018Applicant: Microchip Technology IncorporatedInventors: Bryan Kris, Neil Deutscher, Thomas S. Spohrer
-
Patent number: 10003353Abstract: Embodiments of the present disclosure include voltage comparators. The voltage comparators may include a first input configured to receive a first analog voltage, a second input configured to receive a second analog voltage, a first digital delay line configured to propagate the first analog voltage through a first delay circuit and the second analog voltage through a second circuit, and an output circuit configured to provide a comparator output based upon whether values representing the first analog voltage or the second analog voltage propagated faster through the first digital delay line. The comparator output may be configured to identify whether the first analog voltage or the second analog voltage is greater.Type: GrantFiled: July 18, 2017Date of Patent: June 19, 2018Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Bryan Kris, Jim Bartling, Neil Deutscher
-
Patent number: 9948317Abstract: An analog-to-digital converter includes differential digital delay lines, a circuit including a set of delay elements included in the differential digital delay lines, and another circuit including another set of delay elements included in the differential digital delay lines. The first circuit is configured to generate data representing an analog to digital conversion of an input. The second circuit is configured to calibrate a source to the differential digital delay lines.Type: GrantFiled: April 11, 2017Date of Patent: April 17, 2018Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Bryan Kris, Neil Deutscher
-
Patent number: 9923570Abstract: Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC), comprising differential digital delay lines including series coupled delay cells, wherein a delay time of a first delay line is controlled by a first input of the ADC and a delay time of a second delay line is controlled by a second input of the ADC. The ADC includes a pair of bypass multiplexers coupled at a predefined node location in the series coupled delay cells, latches each coupled with the series coupled delay cells, a converter circuit coupled with the plurality of latches configured to convert data from the latches into an output value of the ADC, and logic circuits configured to select data from the series coupled delay cells to the latches depending on a selected resolution of the differential digital delay line analog-to-digital converter.Type: GrantFiled: April 11, 2017Date of Patent: March 20, 2018Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Bryan Kris, Neil Deutscher, Thomas S. Spohrer
-
Publication number: 20180026648Abstract: Embodiments of the present disclosure include voltage comparators. The voltage comparators may include a first input configured to receive a first analog voltage, a second input configured to receive a second analog voltage, a first digital delay line configured to propagate the first analog voltage through a first delay circuit and the second analog voltage through a second circuit, and an output circuit configured to provide a comparator output based upon whether values representing the first analog voltage or the second analog voltage propagated faster through the first digital delay line. The comparator output may be configured to identify whether the first analog voltage or the second analog voltage is greater.Type: ApplicationFiled: July 18, 2017Publication date: January 25, 2018Applicant: Microchip Technology IncorporatedInventors: Bryan Kris, Jim Bartling, Neil Deutscher
-
Publication number: 20170294921Abstract: Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC), comprising differential digital delay lines including series coupled delay cells, wherein a delay time of a first delay line is controlled by a first input of the ADC and a delay time of a second delay line is controlled by a second input of the ADC. The ADC includes a pair of bypass multiplexers coupled at a predefined node location in the series coupled delay cells, latches each coupled with the series coupled delay cells, a converter circuit coupled with the plurality of latches configured to convert data from the latches into an output value of the ADC, and logic circuits configured to select data from the series coupled delay cells to the latches depending on a selected resolution of the differential digital delay line analog-to-digital converter.Type: ApplicationFiled: April 11, 2017Publication date: October 12, 2017Applicant: Microchip Technology IncorporatedInventors: Bryan Kris, Neil Deutscher, Tom Spohrer
-
Publication number: 20170294919Abstract: Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines, a circuit including a set of delay elements included in the differential digital delay lines, and another circuit including another set of delay elements included in the differential digital delay lines. The first circuit is configured to generate data representing an analog to digital conversion of an input. The second circuit is configured to calibrate a source to the differential digital delay lines.Type: ApplicationFiled: April 11, 2017Publication date: October 12, 2017Applicant: Microchip Technology IncorporatedInventors: Bryan Kris, Neil Deutscher
-
Publication number: 20170294920Abstract: Embodiments of the present disclosure include a microcontroller with a processor, memory, and peripheral devices including a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines, a circuit including a set of delay elements included in the differential digital delay lines, and another circuit including another set of delay elements included in the differential digital delay lines. The first circuit is configured to generate data representing an analog to digital conversion of an input. The second circuit is configured to calibrate a source to the differential digital delay lines.Type: ApplicationFiled: April 11, 2017Publication date: October 12, 2017Applicant: Microchip Technology IncorporatedInventors: Bryan Kris, Neil Deutscher
-
Patent number: 8432140Abstract: An integrated circuit boost regulator design providing selection of either a low power on-chip power component boost regulator circuit or a high power off-chip power component boost regulator circuit using the same integrated circuit device.Type: GrantFiled: February 13, 2012Date of Patent: April 30, 2013Assignee: Microchip Technology IncorporatedInventors: Neil Deutscher, Jinhui Chen, James S. Bartling
-
Patent number: 7852118Abstract: A conditional level shifter circuit is used to substantially eliminate sneak current from occurring in an integrated circuit device having two or more logic circuit modules in different voltage domains. Sneak current is caused when a signal between the two or more logic circuit modules in different voltage domains is at logic “0” and one of the logic circuit modules is biased at a voltage level above the true ground, VSS, of the integrated circuit device. The conditional ground restoration circuit shifts the virtual ground logic “0” to the true ground level. This eliminates sneak current and logic level corruption.Type: GrantFiled: December 2, 2009Date of Patent: December 14, 2010Assignee: Microchip Technology IncorporatedInventors: Neil Deutscher, Jinhui Chen, Marquis Jones
-
Publication number: 20100148818Abstract: A conditional level shifter circuit is used to substantially eliminate sneak current from occurring in an integrated circuit device having two or more logic circuit modules in different voltage domains. Sneak current is caused when a signal between the two or more logic circuit modules in different voltage domains is at logic “0” and one of the logic circuit modules is biased at a voltage level above the true ground, VSS, of the integrated circuit device. The conditional ground restoration circuit shifts the virtual ground logic “0” to the true ground level. This eliminates sneak current and logic level corruption.Type: ApplicationFiled: December 2, 2009Publication date: June 17, 2010Inventors: Neil Deutscher, Jinhui Chen, Marquis Jones
-
Patent number: 6432773Abstract: A merged two transistor memory cell of an EEPROM, and method of fabricating same, is provided. The memory cell includes a substrate and insulating layer formed on the substrate. It also includes a memory transistor having a floating gate and a control gate, and a select transistor having a gate that is shared with the memory transistor. The memory cell is configured so that the shared gate serves both as the control gate of the memory transistor and the wordline of the select transistor. The memory cell further includes an ONO stack film that is disposed between the floating gate and the shared gate. In fabricating the memory, the ONO stack film is formed adjacent to the top and side surfaces of the floating gate. The ONO stack film is also formed so as not to be interposed between a potion of the shared gate that is adjacent to the substrate and the insulating layer.Type: GrantFiled: April 8, 1999Date of Patent: August 13, 2002Assignee: Microchip Technology IncorporatedInventors: Donald S. Gerber, Neil Deutscher, Robert P. Ma
-
Patent number: 6087241Abstract: A method is disclosed for forming narrow thermal silicon dioxide side isolation regions in a semiconductor substrate and MOS or CMOS semiconductor devices fabricated by this method. A thin stress relief layer is used in conjunction with a polysilicon buffering stress relief layer on the surface of a semiconductor substrate prior to the field oxidation process to restrict lateral silicon dioxide expansion thereby permitting the creation of narrow thermal silicon dioxide side isolation regions in the semiconductor substrate. A silicon dioxide layer is also used between an amorphous polysilicon (buffering stress relief) layer and a silicon nitride layer to function as an oxide cap, to avoid undesired pitting of the amorphous polysilicon layer, and to avoid interaction between the silicon nitride and amorphous polysilicon layers in areas of high stress.Type: GrantFiled: April 24, 1998Date of Patent: July 11, 2000Assignee: Microchip Technology IncorporatedInventors: Roger St. Amand, Robert Ma, Neil Deutscher