Abstract: A network interface device comprises a streaming data processing path comprising a first data processing engine and hubs. A first scheduler associated with a first hub controls an output of data by the first hub to the first data processing engine and a second scheduler associated with a second hub controls an output of data by the second hub. The first hub is arranged upstream of the first data processing engine on the data processing path and is configured to receive data from a first upstream data path entity and from a first data processing entity implemented in programmable circuitry via a data ingress interface of the first hub. The first data processing engine is configured to receive data from the first hub, process the received data and output the processed data to the second hub arranged downstream of first data processing engine.

Abstract: Embodiments herein describe a configurable packet processing architecture for a SmartNIC or other network device. The configurable architecture includes a plurality of PPEs which are communicatively coupled using a packet bus. A packet can be processed in each of the PPEs. For example, each packet may be first processed by PPE 1, then PPE 2, then PPE 3, and so forth. Moreover, the results of processing the packet at a PPE 1 may affect the operation performed on the packet when it reaches PPE 2 or PPE 3. Thus, the PPEs form a chain where the results determined by a first PPE when processing the packet can affect or change the operation a second PPE performs when processing the same packet.

Abstract: A method comprises compiling, by a compiler, a received program to provide a compiler output for configuring hardware to implement the received program. The received program relate to packets of data in a memory. The compiling comprising defining by the compiler output a plurality of computational units in the hardware, each of the computational units being configured to receive a packet of data as a stream of words and between a first and a second of the computational units, a first buffer for storing words of a packet and a second buffer for storing data output by the first computational unit.

Abstract: A network interface device comprises a streaming data processing path comprising a first data processing engine and hubs. A first scheduler associated with a first hub controls an output of data by the first hub to the first data processing engine and a second scheduler associated with a second hub controls an output of data by the second hub. The first hub is arranged upstream of the first data processing engine on the data processing path and is configured to receive data from a first upstream data path entity and from a first data processing entity implemented in programmable circuitry via a data ingress interface of the first hub. The first data processing engine is configured to receive data from the first hub, process the received data and output the processed data to the second hub arranged downstream of first data processing engine.

Abstract: A network interface device comprises a first area of trust comprising a first part of the network interface device, the first part comprising one or more first kernels. A second area of trust comprising a second part of the network interface device different to said first part is provided, the second part comprising one or more second kernels. A communication link is provided between the first area of trust and the second area of trust. At least one of the first and second areas of trust is provided with isolation circuitry configured to control which data which is passed to the other of the first and second areas via the communication link.

Abstract: The present specification describes a system for eliminating X-ray crosstalk between a plurality of X-ray scanning systems and passive radiation detectors. The system includes a frequency generator for generating a common operational frequency, a high-energy X-ray source or scanning system coupled with the frequency generator for receiving the common operational frequency and configured to modify the pulse repetition frequency of the high-energy X-ray source or scanning system in order to synchronize with the common operational frequency and a low-energy X-ray scanning system and/or passive radiation detection system coupled with the frequency generator for receiving the common operational frequency and having a processing module configured to remove data associated with the common operational frequency at an instance of time if the high-energy X-ray source or scanning system has emitted X-rays at the instance of time.

Abstract: The present specification describes a system for eliminating X-ray crosstalk between a plurality of X-ray scanning systems and passive radiation detectors. The system includes a frequency generator for generating a common operational frequency, a high-energy X-ray source or scanning system coupled with the frequency generator for receiving the common operational frequency and configured to modify the pulse repetition frequency of the high-energy X-ray source or scanning system in order to synchronize with the common operational frequency and a low-energy X-ray scanning system and/or passive radiation detection system coupled with the frequency generator for receiving the common operational frequency and having a processing module configured to remove data associated with the common operational frequency at an instance of time if the high-energy X-ray source or scanning system has emitted X-rays at the instance of time.

Abstract: A network interface device has a data source, a data sink and an interconnect configured to receive data from the data source and to output data to the data sink. The interconnect has a memory having memory cells. Each memory cell has a width which matches a bus segment width. The memory is configured to receive a first write output with a width corresponding to the bus segment width. The write output comprises first data to be written to a first memory cell of the memory, the first data being from the data source.

Abstract: A network interface device has data path circuitry configured to cause data to be moved into and/or out of the network interface device. The data path circuitry comprises: first circuitry for providing one or more data processing operations; and interface circuitry supporting channels. The channels comprises command channels receiving command information from a plurality of data path circuitry user instances, event channels providing respective command completion information to the plurality of data path user instances; and data channels providing the associated data.

Abstract: A network interface device comprises an input configured to receive a storage response comprising a plurality of packets of data, one or more packets comprising a header part and data to be stored, the header part comprising a transport protocol header and a data storage application header. A first packet processor is configured to receive two or more of said plurality of packets and perform transport protocol processing of the received packets to provide transport protocol processed packets A second packet processor configured to receive the transport protocol processed packets from the first packet processor, to write the data to be stored of the received packets to memory and to provide the data storage application header and a pointer to a location in the memory to which the data has been written.

Abstract: A network interface device has a data source, a data sink and an interconnect configured to receive data from the data source and to output data to the data sink. The interconnect has a memory having memory cells. Each memory cell has a width which matches a bus segment width. The memory is configured to receive a first write output with a width corresponding to the bus segment width. The write output comprises first data to be written to a first memory cell of the memory, the first data being from the data source.

Abstract: A network interface device comprises a first area of trust comprising a first part of the network interface device, the first part comprising one or more first kernels. A second area of trust comprising a second part of the network interface device different to said first part is provided, the second part comprising one or more second kernels. A communication link is provided between the first area of trust and the second area of trust. At least one of the first and second areas of trust is provided with isolation circuitry configured to control which data which is passed to the other of the first and second areas via the communication link.

Abstract: A network interface device comprises a streaming data processing path comprising a first data processing engine and hubs. A first scheduler associated with a first hub controls an output of data by the first hub to the first data processing engine and a second scheduler associated with a second hub controls an output of data by the second hub. The first hub is arranged upstream of the first data processing engine on the data processing path and is configured to receive data from a first upstream data path entity and from a first data processing entity implemented in programmable circuitry via a data ingress interface of the first hub. The first data processing engine is configured to receive data from the first hub, process the received data and output the processed data to the second hub arranged downstream of first data processing engine.

Abstract: A network interface device comprises an input configured to receive a storage response comprising a plurality of packets of data, one or more packets comprising a header part and data to be stored, the header part comprising a transport protocol header and a data storage application header. A first packet processor is configured to receive two or more of said plurality of packets and perform transport protocol processing of the received packets to provide transport protocol processed packets A second packet processor configured to receive the transport protocol processed packets from the first packet processor, to write the data to be stored of the received packets to memory and to provide the data storage application header and a pointer to a location in the memory to which the data has been written.

Abstract: The present specification describes a system for eliminating X-ray crosstalk between a plurality of X-ray scanning systems and passive radiation detectors. The system includes a frequency generator for generating a common operational frequency, a high-energy X-ray source or scanning system coupled with the frequency generator for receiving the common operational frequency and configured to modify the pulse repetition frequency of the high-energy X-ray source or scanning system in order to synchronize with the common operational frequency and a low-energy X-ray scanning system and/or passive radiation detection system coupled with the frequency generator for receiving the common operational frequency and having a processing module configured to remove data associated with the common operational frequency at an instance of time if the high-energy X-ray source or scanning system has emitted X-rays at the instance of time.

Abstract: Embodiments of a row address cache circuit are disclosed that may allow the determination the number of times a row address is used to access a dynamic memory. The row address cache circuit may include a memory, first and second pluralities of counters, and a control circuit. The control circuit may be configured to receive a row address and store the row address in an entry of the memory when the row address has not been previously stored. When the row address has been previously stored in an entry of the memory, the control circuit may be configured to change a value of a counter of the first plurality of counters corresponding the entry. The control circuit may be further configured to change a value of each counter of the second plurality of counters after a pre-determined time interval has elapsed, and initiate a refresh of the dynamic memory.

Abstract: Embodiments of a row address cache circuit are disclosed that may allow the determination the number of times a row address is used to access a dynamic memory. The row address cache circuit may include a memory, first and second pluralities of counters, and a control circuit. The control circuit may be configured to receive a row address and store the row address in an entry of the memory when the row address has not been previously stored. When the row address has been previously stored in an entry of the memory, the control circuit may be configured to change a value of a counter of the first plurality of counters corresponding the entry. The control circuit may be further configured to change a value of each counter of the second plurality of counters after a pre-determined time interval has elapsed, and initiate a refresh of the dynamic memory.

Abstract: Embodiments of a row address cache circuit are disclosed that may allow the determination the number of times a row address is used to access a dynamic memory. The row address cache circuit may include a memory, first and second pluralities of counters, and a control circuit. The control circuit may be configured to receive a row address and store the row address in an entry of the memory when the row address has not been previously stored. When the row address has been previously stored in an entry of the memory, the control circuit may be configured to change a value of a counter of the first plurality of counters corresponding the entry. The control circuit may be further configured to change a value of each counter of the second plurality of counters after a pre-determined time interval has elapsed, and initiate a refresh of the dynamic memory.

Abstract: Embodiments of a row address cache circuit are disclosed that may allow the determination the number of times a row address is used to access a dynamic memory. The row address cache circuit may include a memory, first and second pluralities of counters, and a control circuit. The control circuit may be configured to receive a row address and store the row address in an entry of the memory when the row address has not been previously stored. When the row address has been previously stored in an entry of the memory, the control circuit may be configured to change a value of a counter of the first plurality of counters corresponding the entry. The control circuit may be further configured to change a value of each counter of the second plurality of counters after a pre-determined time interval has elapsed, and initiate a refresh of the dynamic memory.

Abstract: According to an embodiment of the invention, an approach is provided for estimating how a particular user would rate a particular item from a plurality of items. The approach is applicable to any type of items, including rental items such as movies, music and games, and the invention is not limited to any particular type of item. One or more items from the plurality of items that have ratings similar to the particular item are identified. One or more other users are identified that have given ratings to the one or more items that are substantially similar to ratings given by the particular user to the one or more items. An estimation is made of how the particular user would rate the particular item based upon ratings for the particular item given by the one or more other users.