Patents by Inventor Neil E. Wood
Neil E. Wood has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8547178Abstract: A ring oscillator is disclosed. The ring oscillator includes a first tri-path inverter, a second tri-path inverter and a third tri-path inverter. The second tri-path inverter is connected to the first tri-path inverter. The third tri-path inverter is connected to the first and second tri-path inverters to provide feedback for oscillations.Type: GrantFiled: October 7, 2011Date of Patent: October 1, 2013Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Neil E. Wood, Patrick Fleming, Andrew T. Kelly, Bin Li, Daniel M. Pirkl
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Publication number: 20120154058Abstract: A ring oscillator is disclosed. The ring oscillator includes a first tri-path inverter, a second tri-path inverter and a third tri-path inverter. The second tri-path inverter is connected to the first tri-path inverter. The third tri-path inverter is connected to the first and second tri-path inverters to provide feedback for oscillations.Type: ApplicationFiled: October 7, 2011Publication date: June 21, 2012Inventors: Neil E. Wood, Andrew T. Kelly, Bin Li, Daniel M. Pirkl
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Patent number: 7408410Abstract: A bias generation circuit for biasing a differential amplifier is disclosed. The bias generation circuit is coupled to the differential amplifier. After determining a common-mode voltage of a pair of differential outputs from the differential amplifier, the bias generation circuit generates a bias voltage, which is proportional to the determined common-mode voltage, to the differential amplifier such that the common-mode input voltage range of the differential amplifier is extended to as far as the rail-to-rail voltage.Type: GrantFiled: June 2, 2006Date of Patent: August 5, 2008Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventor: Neil E. Wood
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Patent number: 7355447Abstract: A level shifter is disclosed. The level shifter includes a level shifter core circuit and a pull-up control logic circuit. In response to an input signal and an output signal of the level shifter core circuit, the pull-up control logic circuit selectively turns on a transistor within the level shifter core circuit to prevent the occurrence of a strong P-N fight state within the level shifter.Type: GrantFiled: June 2, 2006Date of Patent: April 8, 2008Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Neil E. Wood, Chan Lee, Abbas Kazemzadeh
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Publication number: 20070279132Abstract: A bias generation circuit for biasing a differential amplifier is disclosed. The bias generation circuit is coupled to the differential amplifier. After determining a common-mode voltage of a pair of differential outputs from the differential amplifier, the bias generation circuit generates a bias voltage, which is proportional to the determined common-mode voltage, to the differential amplifier such that the common-mode input voltage range of the differential amplifier is extended to as far as the rail-to-rail voltage.Type: ApplicationFiled: June 2, 2006Publication date: December 6, 2007Inventor: Neil E. Wood
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Publication number: 20070279092Abstract: A level shifter is disclosed. The level shifter includes a level shifter core circuit and a pull-up control logic circuit. In response to an input signal and an output signal of the level shifter core circuit, the pull-up control logic circuit selectively turns on a transistor within the level shifter core circuit to prevent the occurrence of a strong P-N fight state within the level shifter.Type: ApplicationFiled: June 2, 2006Publication date: December 6, 2007Inventors: Neil E. Wood, Chan Lee, Abbas Kazemzadeh
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Method for connecting circuit elements within an integrated circuit for reducing single-event upsets
Patent number: 7269057Abstract: A method for connecting circuit elements within an integrated circuit for reducing single-event upsets is disclosed. The integrated circuit includes a first and second circuit elements that are substantially identical to each other. In order to reduce the single-event upsets to the first and second circuit elements, each of the first and second circuit elements is divided into a first sub-element and a second sub-element. The first sub-element of the first circuit element is connected to the second sub-element of the second circuit element. The second sub-element of the first circuit element is connected to the first sub-element of the second circuit element. As a result, the nodal spacings between the sub-elements within the first and second circuit elements are effectively increased without demanding additional real estate.Type: GrantFiled: April 27, 2005Date of Patent: September 11, 2007Assignee: BAE Systems Information And Electronic Systems Integration Inc.Inventors: Nadim F. Haddad, Neil E. Wood, Adam Bumgarner, Wayne Neiderer, Shankarnarayana Ramaswamy, Scott Doyle, Tri-Minh Hoang -
Patent number: 6696874Abstract: A single-event upset immune flip-flop circuit is disclosed. The single-event upset immune flip-flop circuit includes a first single-event upset immune latch and a second single-event upset immune latch. The first single-event upset immune latch has two inputs and two outputs. The second single-event upset immune latch also has two inputs and two outputs. The two inputs of the second single-event upset immune latch is connected to the two outputs of the first single-event upset immune latch. The state of the first single-event upset immune latch changes only when the signal polarities at both inputs of the first single-event upset immune latch are identical. Similarly, the state of the second single-event upset immune latch changes only when the signal polarities at both inputs of the second single-event upset immune latch are identical.Type: GrantFiled: July 23, 2002Date of Patent: February 24, 2004Assignee: BAE Systems, Information and Electronic Systems Integration, Inc.Inventor: Neil E. Wood
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Publication number: 20040017237Abstract: A single-event upset immune flip-flop circuit is disclosed. The single-event upset immune flip-flop circuit includes a first single-event upset immune latch and a second single-event upset immune latch. The first single-event upset immune latch has two inputs and two outputs. The second single-event upset immune latch also has two inputs and two outputs. The two inputs of the second single-event upset immune latch is connected to the two outputs of the first single-event upset immune latch. The state of the first single-event upset immune latch changes only when the signal polarities at both inputs of the first single-event upset immune latch are identical. Similarly, the state of the second single-event upset immune latch changes only when the signal polarities at both inputs of the second single-event upset immune latch are identical.Type: ApplicationFiled: July 23, 2002Publication date: January 29, 2004Applicant: BAE SystemsInventor: Neil E. Wood
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Publication number: 20040017233Abstract: A single-event upset immune frequency divider circuit is disclosed. The single-event upset immune frequency divider circuit includes a dual-path shift register, a dual-path multiplexor, and a summing circuit. The dual-path shift register has a clock input, one signal input pair and multiple signal output pairs. The dual-path multiplexor has multiple signal input pairs and one output pair. The signal input pairs of the dual-path multiplexor are respectively connected to the signal output pairs of the dual-input shift register. The dual-path multiplexor selects one of the signal output pairs of the dual-path shift register for feeding back into the signal input pair of the dual-path shift register. The summing circuit then sums the signal input pair of the dual-path shift register to generate an output clock signal that is a fraction of the frequency of an input clock signal at the clock input of the dual-path shift register.Type: ApplicationFiled: July 23, 2002Publication date: January 29, 2004Applicant: BAE Systems, Information and Electronic Systems Integration, Inc.Inventor: Neil E. Wood
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Patent number: 6683932Abstract: A single-event upset immune frequency divider circuit is disclosed. The single-event upset immune frequency divider circuit includes a dual-path shift register, a dual-path multiplexor, and a summing circuit. The dual-path shift register has a clock input, one signal input pair and multiple signal output pairs. The dual-path multiplexor has multiple signal input pairs and one output pair. The signal input pairs of the dual-path multiplexor are respectively connected to the signal output pairs of the dual-input shift register. The dual-path multiplexor selects one of the signal output pairs of the dual-path shift register for feeding back into the signal input pair of the dual-path shift register. The summing circuit then sums the signal input pair of the dual-path shift register to generate an output clock signal that is a fraction of the frequency of an input clock signal at the clock input of the dual-path shift register.Type: GrantFiled: July 23, 2002Date of Patent: January 27, 2004Assignee: BAE Systems, Information and Electronic Systems Integration, Inc.Inventor: Neil E. Wood
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Patent number: 6668342Abstract: A clock splitter circuit provides a radiation hardened pair of adjustably non-overlapping complementary clocks. The circuit includes a pair of clock inverter legs. Each clock inverter leg can include an and-or-inverter (AOI) circuit having a first input coupled to an overlap_en signal, a second input coupled to an inverted overlap_en signal, a third input coupled to an inverted first clock input signal, and a fourth input coupled to an second clock input signal that is substantially 180 degrees out of phase with the first clock input signal. Each clock inverter leg can further include an asymmetric variable delay (AVD) circuit having an input coupled to an output of the first AOI circuit and an input coupled to a waitr_signal that can be used to delay and adjust breadth of non-overlap. Each leg can further include a tri-state inverter circuit having a first input coupled to an output of the AVD circuit, and a second input coupled to the inverted first clock input signal.Type: GrantFiled: April 20, 2001Date of Patent: December 23, 2003Assignee: Bae Systems Information and Electronic Systems Integration, Inc.Inventors: Neil E. Wood, Eric J. Hatch
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Publication number: 20010030567Abstract: A clock splitter circuit provides a radiation hardened pair of adjustably non-overlapping complementary clocks. The circuit includes a pair of clock inverter legs. Each clock inverter leg can include an and-or-inverter (AOI) circuit having a first input coupled to an overlap_en signal, a second input coupled to an inverted overlap_en signal, a third input coupled to an inverted first clock input signal, and a fourth input coupled to an second clock input signal that is substantially 180 degrees out of phase with the first clock input signal. Each clock inverter leg can further include an asymmetric variable delay (AVD) circuit having an input coupled to an output of the first AOI circuit and an input coupled to a waitr_signal that can be used to delay and adjust breadth of non-overlap. Each leg can further include a tri-state inverter circuit having a first input coupled to an output of the AVD circuit, and a second input coupled to the inverted first clock input signal.Type: ApplicationFiled: April 20, 2001Publication date: October 18, 2001Inventors: Neil E. Wood, Eric J. Hatch