Abstract: Provided are organic light emitting devices (OLED) comprising an anode; a cathode, and an organic layer between the anode and the cathode, the organic layer comprising a light-emitting dopant within a host material, the light-emitting dopant being an optically active Pt complex comprising a tetradentate ligand; wherein one enantiomer of the optically active Pt complex is present in an enantiomeric excess (ee) of at least 5%. Further provided are OLEDs comprising an anode, a cathode, and an organic layer between the anode and the cathode, the organic layer the organic layer comprising a light-emitting chiral dopant within a chiral host material, the light-emitting chiral dopant being an optically active complex; wherein one enantiomer of the optically active complex of the chiral dopant is present in an ee of at least 5%, and wherein one enantiomer of the chiral host material is present in an ee of at least 5%.

Abstract: A method and apparatus for speeding up the start-up process of a crystal oscillator. The energy required for starting oscillations is inserted to the crystal by a stimulus in the form of a time-variant voltage or current pattern, either periodic or aperiodic. The stimulus is stopped after a pre-established period, then the oscillator continues to operate in its normal mode and completes the start-up process significantly faster, compared to a start-up process not comprising the above stimulus.

Abstract: A method and apparatus for speeding up the start-up process of a crystal oscillator. The energy required for starting oscillations is inserted to the crystal by a stimulus in the form of a time-variant voltage or current pattern, either periodic or aperiodic. The stimulus is stopped after a pre-established period, then the oscillator continues to operate in its normal mode and completes the start-up process significantly faster, compared to a start-up process not comprising the above stimulus.

Abstract: A method for implementing a Semiconductor Integrated Circuit device using Near/Sub-threshold technology with SW programmable adaptive and dynamic forward and reverse bias voltage control using different sensors inside the chip in order to improve speed, reduce leakage and ensure high yield of the final product that operates at an ultra-low power consumption. This method allows achieving ultra-low power solution with reasonable higher speed and insure high yield.

Abstract: A method for implementing a CMOS input buffer that consumes very low current even when input levels are less than full swing. An additional optional stage enables conversion to very low voltage swing. The circuit can be manufactured with a standard CMOS processing technology and with high immunity to variation of process parameters. The circuit provides some hysteresis response, enhancing the input voltage margin.

Abstract: A method for implementing a Semiconductor Integrated Circuit device using Near/Sub-threshold technology with SOFTWARE programmable Adaptive Dynamic Voltage Control (ADVC) algorithm using different sensors inside the chip in order to improve the target speed and reduce the energy per operation of the final product. This method achieves the best power per performance for a given solution operating at a required speed.

Abstract: A method for implementing a programmable critical delay path measurement in-line with the critical path logic cells. Additionally, the delay measurement creates a code to be used with a programmable DLL which indicates the delay of the measured critical path. This code can also be used by an off line First Fail Circuit which can mimic the delay of the critical path and give an indication of the critical path delay. The target of this invention is to create a method to optimize the required operating voltage of an integrated circuit per specific speed requirement, overcoming different process variations, temperatures changes and in die variations.

Abstract: A method and flow for implementing a “clock tree” inside an ASIC using Sub-threshold or Near-threshold technology with optimal power. The invention may also implement concurrently use of two voltage domains inside a single place and route block. One voltage domain for the “clock tree” buffers and one voltage domain for the other cells at the block. The voltage domain for the “clock tree” buffers that is used is slightly higher than the voltage domain which is used for the other cells. The higher voltage ensures a large reduction of the total number of buffers inside the “clock tree” and the dynamic and static power are reduced dramatically despite the use of slightly higher operating voltage.

Abstract: A method and flow for implementing an ASIC using sub-threshold technology with optimized selection of voltage and process for a given application performance. An embodiment may also implement concurrently used multiple voltage domains inside a single place and route block. The voltage domain is dynamically changed between the cells at the placement time based on the timing path requirements.

Abstract: A method for implementing a Semiconductor Integrated Circuit device using Near/Sub-threshold technology with SW programmable adaptive and dynamic forward and reverse bias voltage control using different sensors inside the chip in order to improve speed, reduce leakage and ensure high yield of the final product that operates at an ultra-low power consumption. This method allows achieving ultra-low power solution with reasonable higher speed and insure high yield.

Abstract: A method for implementing a Semiconductor Integrated Circuit device using Near/Sub-threshold technology with SOFTWARE programmable Adaptive Dynamic Voltage Control (ADVC) algorithm using different sensors inside the chip in order to improve the target speed and reduce the energy per operation of the final product. This method achieves the best power per performance for a given solution operating at a required speed.

Abstract: A method and flow for implementing a “clock tree” inside an ASIC using Sub-threshold or Near-threshold technology with optimal power. The invention may also implement concurrently use of two voltage domains inside a single place and route block. One voltage domain for the “clock tree” buffers and one voltage domain for the other cells at the block. The voltage domain for the “clock tree” buffers that is used is slightly higher than the voltage domain which is used for the other cells. The higher voltage ensures a large reduction of the total number of buffers inside the “clock tree” and the dynamic and static power are reduced dramatically despite the use of slightly higher operating voltage.

Abstract: A method and flow for implementing an ASIC using sub-threshold technology with optimized selection of voltage and process for a given application performance. An embodiment may also implement concurrently used multiple voltage domains inside a single place and route block. The voltage domain is dynamically changed between the cells at the placement time based on the timing path requirements.

Abstract: An analog data stream is monitored as a series of blocks. A ring memory array digitally stores the blocks and repetitively loads and unloads the blocks. A freeze switch disables loading of the latest blocks. A block identifier puts out a unique block identification value for each block put out by the memory and is responsive to the freeze switch, so that when loading stops, each block put out bears the same identification value. The invention is particularly well suited to handling of television frames.