Patents by Inventor Neil Feldman

Neil Feldman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10608584
    Abstract: A method and apparatus for speeding up the start-up process of a crystal oscillator. The energy required for starting oscillations is inserted to the crystal by a stimulus in the form of a time-variant voltage or current pattern, either periodic or aperiodic. The stimulus is stopped after a pre-established period, then the oscillator continues to operate in its normal mode and completes the start-up process significantly faster, compared to a start-up process not comprising the above stimulus.
    Type: Grant
    Filed: December 17, 2017
    Date of Patent: March 31, 2020
    Assignee: PLSense Ltd.
    Inventors: Shraga Kraus, Neil Feldman
  • Publication number: 20190190447
    Abstract: A method and apparatus for speeding up the start-up process of a crystal oscillator. The energy required for starting oscillations is inserted to the crystal by a stimulus in the form of a time-variant voltage or current pattern, either periodic or aperiodic. The stimulus is stopped after a pre-established period, then the oscillator continues to operate in its normal mode and completes the start-up process significantly faster, compared to a start-up process not comprising the above stimulus.
    Type: Application
    Filed: December 17, 2017
    Publication date: June 20, 2019
    Applicant: PLSense Ltd.
    Inventors: Shraga Kraus, Neil Feldman
  • Patent number: 10120967
    Abstract: A method for implementing a Semiconductor Integrated Circuit device using Near/Sub-threshold technology with SW programmable adaptive and dynamic forward and reverse bias voltage control using different sensors inside the chip in order to improve speed, reduce leakage and ensure high yield of the final product that operates at an ultra-low power consumption. This method allows achieving ultra-low power solution with reasonable higher speed and insure high yield.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: November 6, 2018
    Assignee: PLSense Ltd.
    Inventors: Uzi Zangi, Neil Feldman
  • Patent number: 9935542
    Abstract: A method for implementing a Semiconductor Integrated Circuit device using Near/Sub-threshold technology with SOFTWARE programmable Adaptive Dynamic Voltage Control (ADVC) algorithm using different sensors inside the chip in order to improve the target speed and reduce the energy per operation of the final product. This method achieves the best power per performance for a given solution operating at a required speed.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: April 3, 2018
    Assignee: PLSense Ltd.
    Inventors: Uzi Zangi, Neil Feldman
  • Patent number: 9935636
    Abstract: A method for implementing a CMOS input buffer that consumes very low current even when input levels are less than full swing. An additional optional stage enables conversion to very low voltage swing. The circuit can be manufactured with a standard CMOS processing technology and with high immunity to variation of process parameters. The circuit provides some hysteresis response, enhancing the input voltage margin.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: April 3, 2018
    Assignee: PLSense Ltd.
    Inventors: Tuvia Liran, Neil Feldman, Uzi Zangi
  • Patent number: 9882564
    Abstract: A method for implementing a programmable critical delay path measurement in-line with the critical path logic cells. Additionally, the delay measurement creates a code to be used with a programmable DLL which indicates the delay of the measured critical path. This code can also be used by an off line First Fail Circuit which can mimic the delay of the critical path and give an indication of the critical path delay. The target of this invention is to create a method to optimize the required operating voltage of an integrated circuit per specific speed requirement, overcoming different process variations, temperatures changes and in die variations.
    Type: Grant
    Filed: March 19, 2017
    Date of Patent: January 30, 2018
    Assignee: PLSENSE Ltd.
    Inventors: Uzi Zangi, Neil Feldman
  • Patent number: 9768775
    Abstract: A method and flow for implementing a “clock tree” inside an ASIC using Sub-threshold or Near-threshold technology with optimal power. The invention may also implement concurrently use of two voltage domains inside a single place and route block. One voltage domain for the “clock tree” buffers and one voltage domain for the other cells at the block. The voltage domain for the “clock tree” buffers that is used is slightly higher than the voltage domain which is used for the other cells. The higher voltage ensures a large reduction of the total number of buffers inside the “clock tree” and the dynamic and static power are reduced dramatically despite the use of slightly higher operating voltage.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: September 19, 2017
    Assignee: PLSense Ltd.
    Inventors: Uzi Zangi, Neil Feldman
  • Patent number: 9531385
    Abstract: A method and flow for implementing an ASIC using sub-threshold technology with optimized selection of voltage and process for a given application performance. An embodiment may also implement concurrently used multiple voltage domains inside a single place and route block. The voltage domain is dynamically changed between the cells at the placement time based on the timing path requirements.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: December 27, 2016
    Assignee: PLSense Ltd.
    Inventors: Uzi Zangi, Neil Feldman
  • Publication number: 20160283630
    Abstract: A method for implementing a Semiconductor Integrated Circuit device using Near/Sub-threshold technology with SW programmable adaptive and dynamic forward and reverse bias voltage control using different sensors inside the chip in order to improve speed, reduce leakage and ensure high yield of the final product that operates at an ultra-low power consumption. This method allows achieving ultra-low power solution with reasonable higher speed and insure high yield.
    Type: Application
    Filed: July 21, 2015
    Publication date: September 29, 2016
    Applicant: PLSense Ltd.
    Inventors: Uzi Zangi, Neil Feldman
  • Publication number: 20160267208
    Abstract: A method for implementing a Semiconductor Integrated Circuit device using Near/Sub-threshold technology with SOFTWARE programmable Adaptive Dynamic Voltage Control (ADVC) algorithm using different sensors inside the chip in order to improve the target speed and reduce the energy per operation of the final product. This method achieves the best power per performance for a given solution operating at a required speed.
    Type: Application
    Filed: March 4, 2016
    Publication date: September 15, 2016
    Applicant: PLSense Ltd.
    Inventors: Uzi Zangi, Neil Feldman
  • Publication number: 20160126954
    Abstract: A method and flow for implementing a “clock tree” inside an ASIC using Sub-threshold or Near-threshold technology with optimal power. The invention may also implement concurrently use of two voltage domains inside a single place and route block. One voltage domain for the “clock tree” buffers and one voltage domain for the other cells at the block. The voltage domain for the “clock tree” buffers that is used is slightly higher than the voltage domain which is used for the other cells. The higher voltage ensures a large reduction of the total number of buffers inside the “clock tree” and the dynamic and static power are reduced dramatically despite the use of slightly higher operating voltage.
    Type: Application
    Filed: October 27, 2015
    Publication date: May 5, 2016
    Applicant: PLSENSE LTD.
    Inventors: Uzi Zangi, Neil Feldman
  • Publication number: 20160105178
    Abstract: A method and flow for implementing an ASIC using sub-threshold technology with optimized selection of voltage and process for a given application performance. An embodiment may also implement concurrently used multiple voltage domains inside a single place and route block. The voltage domain is dynamically changed between the cells at the placement time based on the timing path requirements.
    Type: Application
    Filed: October 9, 2014
    Publication date: April 14, 2016
    Inventors: Uzi Zangi, Neil Feldman
  • Patent number: 4698664
    Abstract: An analog data stream is monitored as a series of blocks. A ring memory array digitally stores the blocks and repetitively loads and unloads the blocks. A freeze switch disables loading of the latest blocks. A block identifier puts out a unique block identification value for each block put out by the memory and is responsive to the freeze switch, so that when loading stops, each block put out bears the same identification value. The invention is particularly well suited to handling of television frames.
    Type: Grant
    Filed: March 4, 1985
    Date of Patent: October 6, 1987
    Assignee: Apert-Herzog Corporation
    Inventors: William E. Nichols, William F. Herzog, Neil Feldman, William Laumeister