Abstract: A computer-implemented method of reducing susceptibility of a circuit design to single event upsets can include determining a susceptibility level of the circuit design to single event upsets, comparing the susceptibility level with a target susceptibility, and selectively applying a mitigation technique to at least one of a plurality of regions of the circuit design when the susceptibility level of the circuit design exceeds the target susceptibility. The circuit design including the mitigated region can be output.

Abstract: A method of detecting an error when loading a programmable integrated circuit (IC) can include detecting a predetermined bit pattern indicating a start of a bitstream within the programmable IC, starting a timer within the programmable IC responsive to detecting the predetermined bit pattern, and determining whether a bitstream load complete condition has occurred prior to expiration of the timer. When the timer expires prior to an occurrence of the bitstream load complete condition, at least one recovery action can be implemented.

Abstract: A cycle basis is efficiently determined for a directed graph. A first depth-first search of the directed graph classifies each of the edges of the directed graph to have a type that is one of a within-tree type for an edge within a tree of the first depth first search, a forward type for an edge skipping forward along the tree, a back type for an edge directed back along the tree, or a cross type for an edge between two subtrees of the tree. A second depth-first search of the directed graph determines a respective cycle for each of the edges of the back type. A third depth-first search of the directed graph determines a respective cycle for each of the edges of the cross type that is included a cycle. The basis is output the basis that specifies each of the respective cycles.

Abstract: A computer-implemented method of verifying electrical isolation of portions of a circuit design for a programmable integrated circuit (IC) can include translating a circuit design into a circuit design bitstream specifying a plurality of regions, wherein the regions are to be isolated from one another. Routing resources of the programmable IC that are not used by the circuit design can be identified. A fence bitstream can be generated that specifies the unused routing resources. The circuit design bitstream can be compared with the fence bitstream. An indication of whether the plurality of regions of the programmable IC are isolated can be output according to the comparison.

Abstract: Methods and apparatus are disclosed for identifying a system. In various embodiments, values of identification codes are read from each of a plurality of electronic devices of the system. The values of the identification codes are used to generate a system identifier value.

Abstract: A memory coupled to a programmable logic device (PLD) is configured through the PLD's JTAG port. A soft core loaded into the PLD connects to the JTAG port and memory. An external programming host device connects to the JTAG port, sends instructions and data to and receives data from the memory via the JTAG port and soft core. A synchronization JTAG instruction is loaded, and a Shift Data state of the JTAG port state machine is used. The programming host device and soft core are synchronized, and a memory chip select is asserted. A memory instruction, such as READ, WRITE or ERASE is loaded into the memory. An RTI state of the state machine is used to wait for instruction completion and the chip select is deasserted. Another instruction is processed starting with using the Shift Data state. Alternatively, a PLD Shift Data Register is used in conjunction with the soft core.

Abstract: Methods and systems are provided for determining a total length of instruction registers. A data shift of a scan chain determines whether each device in the scan chain is an identified device. An overall length of the instruction registers of the devices is determined from an instruction shift. An actual position is determined for an identified device between each pair of sub-sequences of unidentified devices. An instruction shift of the scan chain attempts to set the respective instruction register of the identified device using one or more trial positions. If a data shift of the scan chain obtains the recognized value of the respective identification register of the identified device for one of the trial positions, then this trial position is the actual position within the overall length. The total length is determined for the instruction registers of the unidentified devices in each sub-sequence of the unidentified devices.

Abstract: A PLD includes a plurality of logic blocks, a test circuit, and a test pin set. The logic blocks are coupled to gating circuits that selectively adjust an operating voltage for the blocks in response to control signals. During operation of the PLD, the control signals are updated in response to externally-generated signals provided to the PLD via the test pin set and routed to the logic blocks using the test circuit.

Abstract: Methods and apparatus are disclosed for managing configuration data for a system. In various embodiments, a chain description data set is generated to specify an order in a configuration chain of configurable devices in the system and identify configuration data sets associated with the configurable devices. A system identifier value is generated and associated with the chain description data set. An archive is generated including the configuration data sets, chain description data set, and system identifier value.

Abstract: Provision of configuration access to a programmable device such as a programmable logic device (PLD) via a boundary-scannable devices. In one embodiment a configuration controller is arranged to transfer configuration data that specify configuration access for the PLD. A scan controller is coupled to the configuration controller and arranged to generate boundary-scan signals responsive to configuration data from the configuration controller. At least one boundary-scannable device has a plurality of boundary-scan pins coupled to the scan controller, and a PLD is coupled to the boundary-scannable device.

Abstract: Monitoring of the state vector of a test access port (TAP) permits isolation of the root cause of improper transitions of the state vector due to various factors, including electrical noise. The test access port includes TCK, TMS, TDI, and TDO. A circuit for monitoring the state vector includes a TAP controller, a storage circuit, and a sampling circuit. The TAP controller updates the state vector for each transition of TCK. The storage circuit stores a value of the state vector responsive to transitions of TCK while a write enable is enabled. To permit generating the write enable without additional pins and without violating a protocol for the test access port, the write enable may be generated in response to a plurality of transitions of TDI of the test access port during an interval in which TMS and TCK of the test access port have no transitions.

Abstract: A software architecture for facilitating communications between a computer or workstation and a programming apparatus used to program a PLD by minimizing the number of two-way communications on a standard download cable (e.g., RS232, USB) connected between the computer and the programming apparatus. A first component used to encode programming instructions and configuration data to form a first transmission stream that is transmitted to the programming apparatus in a single, long burst. The programming apparatus includes a second component of the software architecture that interprets the first transmission stream and programs the PLD using, for example, Boundary-Scan signals that are generated in response to the programming instructions and configuration data. A buffer memory stores data shifted out of the PLD during the programming operation, which is transmitted to the computer in a single, long burst after the first transmission stream is completed.

Abstract: Method and system for a programmable device programmer. The disclosure describes various embodiments for programming a target programmable device by a programmer. In one embodiment, the programmer determines availability of updated configuration data for a hardware component of the programmer. The programmer includes the software component coupled to the hardware component. An update mode of the hardware component is enabled in response to availability of the updated configuration data, and programming of the target programmable device is disabled while the hardware component is in the update mode. A programmable device internal to the hardware component is programmed with the updated configuration data while the hardware component is in the update mode, and the update mode is disabled in response to completion of programming of the at least one programmable device. A target programmable device may then be programmed by the programmer having the updated configuration data.

Abstract: A bitstream having a plurality of data sets is provided to an integrated circuit device such as an FPGA having test circuitry capable of routing data to the device's internal resources, with each data set including configuration information and a trigger signal. Successive data sets of the bitstream are sequentially processed by the test circuitry in response to the trigger signals to sequentially initialize the device's resources to various states. For some embodiments, each data set includes configuration data to configure one or more configurable elements of the device to implement a desired design and includes soft data for use by a processor embedded within the device. For one embodiment, control logic is provided to selectively wait for a predetermined time period before processing a next data set.

Abstract: A system and method for diagnosing an electronic device remotely using a network is provided. The electronic device includes one or more programmable logic devices that are configurable. A diagnostic microcontroller functions to communicate to the programmable logic devices and to communicate to the network. To diagnose the electronic device, communication is established to the network and to a diagnostic/repair center. The diagnostic/repair center selects diagnostic commands and transmits them to the electronic device. The diagnostic microcontroller initiates the diagnostic commands on the one or more programmable logic devices to test their configuration and/or functionality. Test results are collected and transmitted back to the diagnostic/repair center for analysis. Based on the analysis, if appropriate, reconfiguration commands are sent to reconfigure the programmable logic device to correct identified errors.

Abstract: Method and apparatus are described for providing analog capability with boundary-scanning for an integrated circuit. The integrated circuit includes a boundary-scan controller (1517) coupled to an analog-to-digital converter (200). An analog channel is selected for input to the analog-to-digital converter (200). Analog information is converted to digital information by the analog-to-digital converter (200), and then such digital information may be stored in data registers (209) for reading out via the boundary-scan controller (1517).

Abstract: Various approaches for indicating completion of configuration of programmable logic devices are disclosed. In one embodiment, a plurality of configuration memory cells are arranged for storage of a configuration bitstream for implementing a circuit design on the programmable logic circuit. A plurality of configurable resources are coupled to the configuration memory cells, and each configurable resource implements a function based on data stored in one or more of the configuration memory cells coupled to the configurable resource. A logic circuit is coupled to a subset of the configuration memory cells and is configured to assert a done signal in response to states of the subset of the configuration memory cells.

Abstract: A flexible architecture for extending the instruction set for a boundary-scan interface. An instruction can be selected from a memory store (308) and decoded by a decoder (310). The instruction can subsequently be shifted into an instruction register (349) where it can be executed. Alternatively, a length of an existing instruction register (382) of a boundary-scan interface can be programmably appended to effectively increase the length of the register. A plurality of serially arranged bit registers (376, 378, 380) can be connected in series with the existing instruction register. By selecting an outer one of the serially arranged bit registers, the length of the existing instruction register can be extended.

Abstract: A method for programming a series of in-system programmable devices that uses Boundary-Scan techniques to read device identification codes from each device of a system, and to automatically generate a board/device information file including a record for each device arranged in the order in which the devices are chained in the system. The device identification codes are then used to automatically retrieve device specifications from a central database. When no identification code is provided from the device, or the database fails to include specifications for a particular device, the user is prompted to enter minimum information or specifications necessary to carry out communications with the device. After device specifications are entered for each device, the user is prompted to enter configuration data, which is automatically matched to its associated device, and compared for consistency with the device specifications.

Abstract: Various approaches for converting configuration data for programmable circuits are disclosed. In one embodiment, a first configuration bitstream is provided. The first configuration bitstream has a format compatible with a first protocol for communicating with and configuring the programmable circuit. A second protocol is selected for communicating with and configuring the programmable circuit, and the first configuration bitstream is converted to a second configuration bitstream. The second configuration bitstream has a format compatible with the second protocol. The programmable circuit is configured with the second configuration bitstream.