Abstract: A device and method for independent control of SDRAM memory in an SDRAM memory module. The device includes an in-line controller (ILC) coupled to receive indications of memory controller interrupt events. The ILC is coupled with the SDRAM memory, possibly through a registered buffer, in such a way that when an indication of a memory controller interrupt event is received, the ILC issues appropriate instructions to the SDRAM memory and prevents any spurious memory controller signals from being transmitted along the control bus. A memory module incorporating an ILC in communication with a memory controller and an SDRAM memory device or bank of such devices. Ultimately, a number of ILCs may be used, each controlling an individual SDRAM bank or discreet memory device.