Abstract: For use in systems having multiple potential clock sources, circuitry and methods are used for selecting from among multiple clock sources and for preventing switching to an inactive clock source. Such clock switching circuitry and methods are used to detect an activity-status indication of the clock sources, generate a selection based update-enable signal responsive to the detected activity-status indication of the selected clock source, update a clock select input signal in response to a clock switch request for switching to the selected clock source and based on the generated selection based update-enable signal, and control switching to the selected clock source based on the updated clock select input signal.

Abstract: For use in systems having multiple potential clock sources, circuitry and methods are used for selecting from among multiple clock sources and for preventing switching to an inactive clock source. Such clock switching circuitry and methods are used to detect an activity-status indication of the clock sources, generate a selection based update-enable signal responsive to the detected activity-status indication of the selected clock source, update a clock select input signal in response to a clock switch request for switching to the selected clock source and based on the generated selection based update-enable signal, and control switching to the selected clock source based on the updated clock select input signal.

Abstract: A circuit arrangement including a test-traffic generator, and adapted to communicate test-traffic onto a digital data path having other traffic sources. A first embodiment includes a data-generation circuit, a memory arrangement, state machine circuitry, and a status and feedback circuit. The memory arrangement stores a plurality of programmable commands indicative the type, pattern and behavior-in-time of the test-traffic. The data-generation circuit provides a data stream to the state machine circuitry, where the state machine assembles portions of the data stream into test-traffic having type, pattern and behavior-in-time characteristics selected responsive to the programmable commands. The state machine generates test-traffic on the digital data path. The status and feedback circuit monitors the digital data path for test-traffic, verifies the test-traffic against the data stream, and generates a feedback signal indicative of test-traffic quality or throughput.

Abstract: A circuit arrangement including a test-traffic generator, and adapted to communicate test-traffic onto a digital data path having other traffic sources. A first embodiment includes a data-generation circuit, a memory arrangement, state machine circuitry, and a status and feedback circuit. The memory arrangement stores a plurality of programmable commands indicative the type, pattern and behavior-in-time of the test-traffic. The data-generation circuit provides a data stream to the state machine circuitry, where the state machine assembles portions of the data stream into test-traffic having type, pattern and behavior-in-time characteristics selected responsive to the programmable commands. The state machine generates test-traffic on the digital data path. The status and feedback circuit monitors the digital data path for test-traffic, verifies the test-traffic against the data stream, and generates a feedback signal indicative of test-traffic quality or throughput.