Abstract: The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMA) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.

Abstract: An interrupt interface of a central processing unit (CPU) comprises a bus with a plurality of interfaces to various components of the CPU. These components can include a memory that includes instructions to execute operations of a processor component, a plurality of virtual machines (VMs) and a virtual machine monitor (VMM)/hypervisor configured to execute the plurality of VMs. The processor can receive interrupt requests (interrupt) as service requests in parallel, which can be executed by the VMM or any one or more of the plurality of VMs to execute VM applications on a dedicated instance of a guest operating system for a task. The processor can further determine whether to grant an interrupt request to the VMM and the VMs based on predetermined criteria, including a current task priority, a pending interrupt priority, or an interrupt enable, associated with the current status of each of the component.

Abstract: An interrupt interface of a central processing unit (CPU) comprises a bus with a plurality of interfaces to various components of the CPU. These components can include a memory that includes instructions to execute operations of a processor component, a plurality of virtual machines (VMs) and a virtual machine monitor (VMM)/hypervisor configured to execute the plurality of VMs. The processor can receive interrupt requests (interrupt) as service requests in parallel, which can be executed by the VMM or any one or more of the plurality of VMs to execute VM applications on a dedicated instance of a guest operating system for a task. The processor can further determine whether to grant an interrupt request to the VMM and the VMs based on predetermined criteria, including a current task priority, a pending interrupt priority, or an interrupt enable, associated with the current status of each of the component.

Abstract: A system and method for increasing lockstep core availability provides for writing a state of a main CPU core to a state buffer, executing one or more instructions of a task by the main CPU core to generate a first output for each executed instruction, and executing the one or more instructions of the task by a checker CPU core to generate a second output for each executed instruction. The method further includes comparing the first output with the second output, and if the first output does not match the second output, generating one or more control signals, and based upon the generation of the one or more control signals, loading the state of the main CPU core from the state buffer to the main CPU core and the checker CPU core.

Abstract: The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMA) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.

Abstract: The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMY) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.

Abstract: The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMY) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.

Abstract: Embodiments relate to systems and methods for detecting register corruption within CPUs operating on the same input data enabling non-invasive read access to and comparison of contents of at least one set of according ones of registers of different CPUs to detect corrupted registers in form of according registers with inconsistent contents.

Abstract: A system and method for processing data for use with a microcontroller having a processing unit provides for sending an input data address to a memory as part of a read request for input data stored in the memory, receiving the input data from the memory, generating a plurality of trace signals, generating a first plurality of signatures based upon the plurality of trace signals, receiving a second plurality of corresponding signatures from a second microcontroller, comparing each signature of the first plurality of signatures to each corresponding signature of the second plurality of corresponding signatures, generating a first error signal if the comparison produces at least one mismatch, and utilizing the first error signal to generate one or more disable signals for disabling operation of one or more devices under control of the microcontroller.

Abstract: A system and method for increasing lockstep core availability provides for writing a state of a main CPU core to a state buffer, executing one or more instructions of a task by the main CPU core to generate a first output for each executed instruction, and executing the one or more instructions of the task by a checker CPU core to generate a second output for each executed instruction. The method further includes comparing the first output with the second output, and if the first output does not match the second output, generating one or more control signals, and based upon the generation of the one or more control signals, loading the state of the main CPU core from the state buffer to the main CPU core and the checker CPU core.

Abstract: Embodiments relate to systems and methods for detecting register corruption within CPUs operating on the same input data enabling non-invasive read access to and comparison of contents of at least one set of according ones of registers of different CPUs to detect corrupted registers in form of according registers with inconsistent contents.

Abstract: The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous.

Abstract: Processors, microprocessors and logical block systems and methods, error detection systems and methods, and integrated circuits are disclosed. In an embodiment, a logic-based computing system includes a first processing core; a second processing core generated from the first processing core and including an inverted logical equivalent of the first processing core such that an output of the second processing core is a complement of an output of the first processing core; and comparator logic coupled to receive the outputs of the first and second processing cores as inputs and provide an error output if the output of the second processing core is not the complement of the output of the first processing core.

Abstract: A system and method for processing data for use with a microcontroller having a processing unit provides for sending an input data address to a memory as part of a read request for input data stored in the memory, receiving the input data from the memory, generating a plurality of trace signals, generating a first plurality of signatures based upon the plurality of trace signals, receiving a second plurality of corresponding signatures from a second microcontroller, comparing each signature of the first plurality of signatures to each corresponding signature of the second plurality of corresponding signatures, generating a first error signal if the comparison produces at least one mismatch, and utilizing the first error signal to generate one or more disable signals for disabling operation of one or more devices under control of the microcontroller.

Abstract: The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous.

Abstract: Processors, microprocessors and logical block systems and methods, error detection systems and methods, and integrated circuits are disclosed. In an embodiment, a logic-based computing system includes a first processing core; a second processing core generated from the first processing core and including an inverted logical equivalent of the first processing core such that an output of the second processing core is a complement of an output of the first processing core; and comparator logic coupled to receive the outputs of the first and second processing cores as inputs and provide an error output if the output of the second processing core is not the complement of the output of the first processing core.

Abstract: Embodiments relate to systems and methods for reading from and writing to interface peripherals or other shared resources during robust computation utilizing temporally separated redundant execution. Embodiments can be utilized in safety-relevant applications related to automotive, banking and finance, aerospace, defense, Internet payment, and others.

Abstract: The invention relates to a microprocessor device and to a branch prediction method that determines which of a plurality of predetermined branch classes a respective branch instruction to be executed is assigned to, and determines whether the branch is likely to be taken or not, depending on the branch class determined. Advantageously, a respective adaptive branch prediction device assigned to the determined branch class is used for determining whether the branch is likely to be taken or not.

Abstract: A method and system of controlling out of order execution pipelines using pipeline skew parameters is disclosed. The pipeline skew parameters track the relative position of a load/store instruction in a load/store pipeline and a simultaneously issued integer instruction in a variable length integer pipeline. The pipeline skew parameters are used to improve data hazard detection, pipeline stalling, and instruction cancellation.

Abstract: A method and system of controlling out of order execution pipelines using issue tags is disclosed. The issue tags are used to dynamically calculate pipeline skew parameters that track the relative position of a load/store instruction in a load/store pipeline and a simultaneously issued integer instruction in a variable length integer pipeline. The issue tags and pipeline skew parameters are used to improve data hazard detection, pipeline stalling, and instruction cancellation.