Patents by Inventor Neil Leslie Robertson

Neil Leslie Robertson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10868245
    Abstract: A phase change memory device includes a phase change material portion located between a first electrode and a second electrode, and a crystallization template material portion located between the first electrode and the second electrode in contact with the phase change material portion. The crystallization template material portion and the phase change material portion belong to a same crystal system and have matching lattice spacing, or the crystallization template material portion and the phase change material portion do not belong to the same crystal system, but have a matching translational symmetry along at least one paired lattice plane with a matching lattice spacing.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: December 15, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhaoqiang Bai, Mac Apodaca, Michael Grobis, Michael Nicolas Albert Tran, Neil Leslie Robertson, Gerardo Bertero
  • Publication number: 20200388752
    Abstract: A phase change memory device includes a phase change material portion located between a first electrode and a second electrode, and a crystallization template material portion located between the first electrode and the second electrode in contact with the phase change material portion. The crystallization template material portion and the phase change material portion belong to a same crystal system and have matching lattice spacing, or the crystallization template material portion and the phase change material portion do not belong to the same crystal system, but have a matching translational symmetry along at least one paired lattice plane with a matching lattice spacing.
    Type: Application
    Filed: June 5, 2019
    Publication date: December 10, 2020
    Inventors: Zhaoqiang BAI, Mac APODACA, Michael GROBIS, Michael Nicolas Albert TRAN, Neil Leslie ROBERTSON, Gerardo BERTERO
  • Publication number: 20200365204
    Abstract: Systems and methods for improving the crystallization of a phase change material of a phase change memory cell are described. A two-step SET pulse may be applied to the phase change material in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.
    Type: Application
    Filed: June 26, 2020
    Publication date: November 19, 2020
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Zhaoqiang Bai, Mac D. Apodaca, Michael K. Grobis, Michael Nicolas Albert Tran, Neil Leslie Robertson, Gerardo A. Bertero
  • Publication number: 20200365203
    Abstract: Systems and methods for improving the crystallization of a phase change material of a phase change memory cell are described. A two-step SET pulse may be applied to the phase change material in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.
    Type: Application
    Filed: May 14, 2019
    Publication date: November 19, 2020
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Zhaoqiang Bai, Mac D. Apodaca, Michael K. Grobis, Michael Nicolas Albert Tran, Neil Leslie Robertson, Gerardo A. Bertero
  • Patent number: 10839897
    Abstract: Systems and methods for improving the crystallization of a phase change material of a phase change memory cell are described. A two-step SET pulse may be applied to the phase change material in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: November 17, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Zhaoqiang Bai, Mac D. Apodaca, Michael K. Grobis, Michael Nicolas Albert Tran, Neil Leslie Robertson, Gerardo A. Bertero
  • Patent number: 10211393
    Abstract: An MRAM memory cell is proposed that is based on spin accumulation torque. One embodiment includes a magnetic tunnel junction, a spin accumulation layer connected to the magnetic tunnel junction and a polarization layer connected to the spin accumulation layer. The polarization layer and the spin accumulation layer use spin accumulation to provide a spin accumulation torque on the free magnetic layer of the magnetic tunnel junction to change direction of magnetization of the free magnetic layer.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: February 19, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Goran Mihajlovic, Neil Smith, Jordan Asher Katine, Neil Leslie Robertson
  • Patent number: 10157656
    Abstract: A magnetic memory cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M1, and a second conductor M2 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M1, M2 is formed of a magnetic material, and the conductor M2 is more conductive than conductor M1. Steering of current is provided for programming the magnetic memory cell.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: December 18, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Zvonimir Z. Bandic, Jeffery Robinson Childress, Luiz M. Franca-Neto, Jordan Asher Katine, Neil Leslie Robertson
  • Publication number: 20180240966
    Abstract: An MRAM memory cell is proposed that is based on spin accumulation torque. One embodiment includes a magnetic tunnel junction, a spin accumulation layer connected to the magnetic tunnel junction and a polarization layer connected to the spin accumulation layer. The polarization layer and the spin accumulation layer use spin accumulation to provide a spin accumulation torque on the free magnetic layer of the magnetic tunnel junction to change direction of magnetization of the free magnetic layer.
    Type: Application
    Filed: February 23, 2017
    Publication date: August 23, 2018
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Goran Mihajlovic, Neil Smith, Jordan Asher Katine, Neil Leslie Robertson
  • Patent number: 9780143
    Abstract: A magnetic memory integrated with complementary metal oxide semiconductor (CMOS) driving circuits and a method for implementing magnetic memory integrated with complementary metal oxide semiconductor (CMOS) driving circuits for use in Solid-State Drives (SSDs) are provided. A complementary metal oxide semiconductor (CMOS) wafer is provided, and a magnetic memory is formed on top of the CMOS wafer providing a functioning magnetic memory chip.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: October 3, 2017
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Zvonimir Z. Bandic, Jeffery Robinson Childress, Luiz M. Franca-Neto, Jordan Asher Katine, Neil Leslie Robertson
  • Patent number: 9673387
    Abstract: A magnetic memory pillar cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M1, and a second conductor M2, the second conductor M1 surrounded by the first conductor M1 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M1, M2 is formed of a magnetic material, and the conductor M2 is more conductive than conductor M1. An oxide barrier extends between the first conductor M1 and a programmable input to the magnetic memory pillar cell; and the oxide barrier is unpatterned.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: June 6, 2017
    Assignee: Western Digital Technologies, Inc.
    Inventors: Zvonimir Z. Bandic, Jeffery Robinson Childress, Luiz M. Franca-Neto, Jordan Asher Katine, Neil Leslie Robertson
  • Publication number: 20170084827
    Abstract: A magnetic memory pillar cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M1, and a second conductor M2, the second conductor M1 surrounded by the first conductor M1 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M1, M2 is formed of a magnetic material, and the conductor M2 is more conductive than conductor M1. An oxide barrier extends between the first conductor M1 and a programmable input to the magnetic memory pillar cell; and the oxide barrier is unpatterned.
    Type: Application
    Filed: December 5, 2016
    Publication date: March 23, 2017
    Inventors: Zvonimir Z. Bandic, Jeffery Robinson Childress, Luiz M. Franca-Neto, Jordan Asher Katine, Neil Leslie Robertson
  • Publication number: 20170062034
    Abstract: A magnetic memory cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M1, and a second conductor M2 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M1, M2 is formed of a magnetic material, and the conductor M2 is more conductive than conductor M1. Steering of current is provided for programming the magnetic memory cell.
    Type: Application
    Filed: August 25, 2015
    Publication date: March 2, 2017
    Inventors: Zvonimir Z. Bandic, Jeffery Robinson Childress, Luiz M. Franca-Neto, Jordan Asher Katine, Neil Leslie Robertson
  • Publication number: 20170062519
    Abstract: A magnetic memory integrated with complementary metal oxide semiconductor (CMOS) driving circuits and a method for implementing magnetic memory integrated with complementary metal oxide semiconductor (CMOS) driving circuits for use in Solid-State Drives (SSDs) are provided. A complementary metal oxide semiconductor (CMOS) wafer is provided, and a magnetic memory is formed on top of the CMOS wafer providing a functioning magnetic memory chip.
    Type: Application
    Filed: August 25, 2015
    Publication date: March 2, 2017
    Inventors: Zvonimir Z. Bandic, Jeffery Robinson Childress, Luiz M. Franca-Neto, Jordan Asher Katine, Neil Leslie Robertson
  • Patent number: 9520444
    Abstract: A magnetic memory pillar cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M1, and a second conductor M2, the second conductor M1 surrounded by the first conductor M1 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M1, M2 is formed of a magnetic material, and the conductor M2 is more conductive than conductor M1. An oxide barrier extends between the first conductor M1 and a programmable input to the magnetic memory pillar cell; and the oxide barrier is unpatterned.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: December 13, 2016
    Assignee: Western Digital Technologies, Inc.
    Inventors: Zvonimir Z. Bandic, Jeffery Robinson Childress, Luiz M. Franca-Neto, Jordan Asher Katine, Neil Leslie Robertson
  • Patent number: 9443905
    Abstract: A three-dimensional (3D) scalable magnetic memory array and a method for implementing the three-dimensional (3D) scalable magnetic memory array for use in Solid-State Drives (SSDs) are provided. A three-dimensional (3D) scalable magnetic memory array includes an interlayer dielectric (IDL) stack of word planes separated by a respective IDL. A plurality of pillar holes is formed in the IDL stack in a single etch step; each of the pillar holes including an oxide barrier coating, and a first conductor M1, and a second conductor M2 forming magnetic pillar memory cells. The first conductor M1 is formed of a magnetic material, and the second conductor M2 is more electrically conductive than the conductor M1; and each of the magnetic pillar memory cell inside the pillar holes have a programmable area using unpatterned programmable magnetic media proximate to a respective one of the word planes.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: September 13, 2016
    Assignee: HGST Netherlands B.V.
    Inventors: Zvonimir Z. Bandic, Jeffery Robinson Childress, Luiz M. Franca-Neto, Jordan Asher Katine, Neil Leslie Robertson
  • Patent number: 9236069
    Abstract: A method for making a current-perpendicular-to-the-plane magnetoresistive sensor structure produces a top electrode that is “self-aligned” on the top of the sensor and with a width less than the sensor trackwidth. A pair of walls of ion-milling resistant material are fabricated to a predetermined height above the biasing layers at the sensor side edges. A layer of electrode material is then deposited onto the top of the sensor between the two walls. The walls serve as a mask during angled ion milling to remove outer portions of the electrode layer. The height of the walls and the angle of ion milling determines the width of the resulting top electrode. This leaves the reduced-width top electrode located on the sensor. Because of the directional ion milling using walls that are aligned with the sensor side edges, the reduced-width top electrode is self-aligned in the center of the sensor.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: January 12, 2016
    Assignee: HGST Netherlands B.V.
    Inventors: Patrick Mesquita Braganca, Jeffrey R. Childress, Jordan Asher Katine, Yang Li, Neil Leslie Robertson, Neil Smith, Petrus Antonius VanDerHeijden, Douglas Johnson Werner
  • Patent number: 9047908
    Abstract: A heat-assisted magnetic recording (HAMR) head in which the core of the optical waveguide has an end face that abuts the NFT and the write pole lip has a diffusion barrier between the end face of the waveguide core and the write pole lip. The diffusion barrier layer may also be located between the waveguide core end face and the NFT, in which case it is formed of an optically transparent material, like TaNx, TiNx, ZrNx, HfNx, NbNx, CrNx, VNx, TiC, TaC, WC, SiC or SiNx, or a layer of Au, Ru, Rh or Ir with a thickness less than 5 nm. In addition to being located between both the NFT and the write pole lip and the waveguide core end face, the diffusion barrier layer may also be located between the waveguide core and the lower waveguide cladding layer.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: June 2, 2015
    Assignee: HGST Netherlands B.V.
    Inventors: Vijay Prakash Singh Rawat, Neil Leslie Robertson
  • Patent number: 8988833
    Abstract: A current-perpendicular-to-the plane magnetoresistive sensor has top and bottom electrodes narrower than the sensor trackwidth. The electrodes are formed of one of Cu, Au, Ag and AgSn, which have an ion milling etch rate much higher than the etch rates for the sensor's ferromagnetic materials. Ion milling is performed at a high angle relative to a line orthogonal to the plane of the electrode layers and the layers in the sensor stack. Because of the much higher etch rate of the material of the top and bottom electrode layers, the electrode layers will have side edges that are recessed from the side edges of the free layer. This reduces the surface areas for the top and bottom electrodes, which causes the sense current passing through the sensor's free layer to be confined in a narrower channel, which is equivalent to having a sensor with narrower physical trackwidth.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: March 24, 2015
    Assignee: HGST Netherlands B.V.
    Inventors: Patrick Mesquita Braganca, Jeffrey R. Childress, Jordan Asher Katine, Yang Li, Neil Leslie Robertson, Neil Smith, Petrus Antonius VanDerHeijden, Douglas Johnson Werner
  • Publication number: 20140340791
    Abstract: A current-perpendicular-to-the plane magnetoresistive sensor has top and bottom electrodes narrower than the sensor trackwidth. The electrodes are formed of one of Cu, Au, Ag and AgSn, which have an ion milling etch rate much higher than the etch rates for the sensor's ferromagnetic materials. Ion milling is performed at a high angle relative to a line orthogonal to the plane of the electrode layers and the layers in the sensor stack. Because of the much higher etch rate of the material of the top and bottom electrode layers, the electrode layers will have side edges that are recessed from the side edges of the free layer. This reduces the surface areas for the top and bottom electrodes, which causes the sense current passing through the sensor's free layer to be confined in a narrower channel, which is equivalent to having a sensor with narrower physical trackwidth.
    Type: Application
    Filed: May 16, 2013
    Publication date: November 20, 2014
    Applicant: HGST Netherlands B.V.
    Inventors: Patrick Mesquita Braganca, Jeffrey R. Childress, Jordan Asher Katine, Yang Li, Neil Leslie Robertson, Neil Smith, Petrus Antonius VanDerHeijden, Douglas Johnson Werner
  • Publication number: 20140313872
    Abstract: A heat-assisted magnetic recording (HAMR) head in which the core of the optical waveguide has an end face that abuts the NFT and the write pole lip has a diffusion barrier between the end face of the waveguide core and the write pole lip. The diffusion barrier layer may also be located between the waveguide core end face and the NFT, in which case it is formed of an optically transparent material, like TaNx, TiNx, ZrNx, HfNX, NbNx, CrNx, VNx, TiC, TaC, WC, SiC or SiNx, or a layer of Au, Ru, Rh or Ir with a thickness less than 5 nm. In addition to being located between both the NFT and the write pole lip and the waveguide core end face, the diffusion barrier layer may also be located between the waveguide core and the lower waveguide cladding layer.
    Type: Application
    Filed: April 23, 2013
    Publication date: October 23, 2014
    Applicant: HGST Netherlands B.V.
    Inventors: Vijay Prakash Singh Rawat, Neil Leslie Robertson