Abstract: A semiconductor integrated circuit and a computing system including the same are provided. The semiconductor integrated circuit includes: an integrated clock gating cell including a clock output node; and clock-based cells each including a clock input node. The clock output node of the integrated clock gating cell and the clock input nodes of the clock-based cells are aligned on a straight line and commonly connected to a clock gating path.

Abstract: Latches in a net of a simulated integrated circuit design are initialized to known logical states prior to application of a reset signal at the beginning of the simulation. The logical states may be set by generating a list of the latches, sorting them in random order, and then dividing them into two groups based on the random order with high and low logical states respectively assigned to the two groups. In a specific implementation the latch states are set using an HDL force command prior to applying the reset signal, and the force command is removed after applying the reset signal using an HDL release command. If the circuit description is a gate-level netlist, then logical states of gates within the storage elements are also set.

Abstract: Latches in a net of a simulated integrated circuit design are initialized to known logical states prior to application of a reset signal at the beginning of the simulation. The logical states may be set by generating a list of the latches, sorting them in random order, and then dividing them into two groups based on the random order with high and low logical states respectively assigned to the two groups. In a specific implementation the latch states are set using an HDL force command prior to applying the reset signal, and the force command is removed after applying the reset signal using an HDL release command. If the circuit description is a gate-level netlist, then logical states of gates within the storage elements are also set.

Abstract: An information handling system including a divider circuit is disclosed that divides an input clock signal by a non integer value to generate an output clock signal. The resultant output clock signal exhibits a 50/50 duty cycle in one embodiment. The disclosed divider methodology permits the design of advanced circuit functions, such as double data rate memory operations, without the need for additional clock signal sources.

Abstract: An information handling system including a divider circuit is disclosed that divides an input clock signal by a non integer value to generate an output clock signal. The resultant output clock signal exhibits a 50/50 duty cycle in one embodiment. The disclosed divider methodology permits the design of advanced circuit functions, such as double data rate memory operations, without the need for additional clock signal sources.

Abstract: An apparatus, a method, and a computer program product are provided for producing a synchronous divider reset signal. A notorious concern with multiple non-integer frequency ratio synchronous source clocks has been the time of edge alignment between the respective clocks. To address this concern, a number of latches can be utilized in order to detect alignment of the edges of these clocks. Specifically, the latches are employed to assist in the production of a synchronous divider reset signal for downstream dividers that are utilized in many microprocessors today. Hence, all of the downstream dividers can be properly synchronized to alleviate any errors that can occur between respective macros of a microprocessor chip resulting from misalignment of clock edges.