Abstract: During verification of a description of a circuit containing a pre-determined assertion, in order to detect incorrect behavior of the circuit that may be caused by metastability occurring in signals that cross clock domains (“CDC” signals) in the circuit, the description of the circuit is automatically transformed by addition of circuitry to inject the effects of metastability into the CDC signals. The transformed description containing the circuitry to inject metastability is verified in the normal manner. Certain embodiments analyze the transformed description using a model checking method to determine a stimulus sequence that will cause the pre-determined assertion to be violated. The transformed circuit is then simulated in some embodiments, using the stimulus sequence from model checking, and an incorrect behavior of the circuit due to metastability is displayed, for diagnosis by the circuit designer. The circuit designer may revise the circuit description and iterate as noted above.

Abstract: During verification of a description of a circuit containing a pre-determined assertion, in order to detect incorrect behavior of the circuit that may be caused by metastability occurring in signals that cross clock domains (“CDC” signals) in the circuit, the description of the circuit is automatically transformed by addition of circuitry to inject the effects of metastability into the CDC signals. The transformed description containing the circuitry to inject metastability is verified in the normal manner. Certain embodiments analyze the transformed description using a model checking method to determine a stimulus sequence that will cause the pre-determined assertion to be violated. The transformed circuit is then simulated in some embodiments, using the stimulus sequence from model checking, and an incorrect behavior of the circuit due to metastability is displayed, for diagnosis by the circuit designer. The circuit designer may revise the circuit description and iterate as noted above.