Abstract: Disclosed is an improved phase detector apparatus which includes a charge pump. The charge pump includes a first integrating node and a second integrating node. The first and second integrating nodes generate node voltages which ramp downward and upward during a given period of a reference signal. When a signal is received to which a reference signal is to be locked on, the integrating sequence of the first and second nodes is altered so that the differential voltage across the nodes indicates a difference in phase between the reference signal and the second signal. A filter is connected between the output signal and the first integrating node, while the second integrating node is referenced to a DC bias level and returns to that level at the beginning and end of each cycle. The charge pump apparatus is driven by variable current sources which give the apparatus a variable frequency response.

Abstract: An improved phase detector apparatus which includes a charge pump. The charge pump includes a first integrating node and a second integrating node. The first and second integrating nodes generate node voltages which ramp downward and upward during a given period of a reference signal. When a signal is received to which a reference signal is to be locked on, the integrating sequence of the first and second nodes is altered so that the differential voltage across the nodes indicates a difference in phase between the reference signal and the second signal. A filter is connected between the output signal and the first integrating node, while the second integrating node is referenced to a DC bias level and returns to that level at the beginning and end of each cycle. The charge pump apparatus is driven by variable current sources which give the apparatus a variable frequency response.

Abstract: Disclosed is an apparatus for synchronizing a first signal with a second signal comprising a plurality of delay means D.sub.i as i goes from 1 to N, where N is an integer, each delay means D.sub.i having an input I.sub.i and a delay output O.sub.i for delaying a signal received at the respective input I.sub.i by an increment .delta.t of time in supplying the delayed signal at the respective delay output O.sub.i. The first delay means D.sub.1 of the plurality of delay means is connected to receive the first signal at its input I.sub.1. Each of the other delay means D.sub.i, for i equal to 2 to N, are connected in series such that the respective input I.sub.i is connected to receive the delay output O.sub.i-1 of the preceding delay means D.sub.i-1. A plurality of latch means L.sub.i, as i goes from 1 to N, are connected to be clocked by the second signal. Each of the latch means L.sub.i latches the signal at the delay output O.sub. i respectively for each of the delay means D.sub.

Abstract: The present invention discloses a low order charge-pump filter operable with a single variable current source. The integrating capacitor of the charge-pump is connected in an H-bridge switching configuration with four switches that are operable to control the current source to supply current to a first node of the capacitor or to a second node of the capacitor or to bypass a capacitor, depending on the state of operation of the charge-pump. The charge-pump filter disclosed is particularly useful for providing the low order response for a phase detector in a phase-locked loop.

Abstract: A phase detector for detecting in real time the difference in phase between frequency pulse signals and data pulse signals, including a control signal generator for generating control signals corresponding to the occurrence of the frequency pulse signals and the occurrence or non-occurrence of the data pulse signals, and a circuit, operative during the occurrence or non-occurrence of the data pulse signals, for producing a phase error signal indicating differences between the real time occurrence of the frequency pulse signals and the data pulse signals. Another circuit of the phase detector, if needed, responds to the control signals to correct the integral of the phase error signal.

Abstract: Disclosed is a circuit providing a controllable effective resistance which comprises of transistor means that provides current at an input node responsive to an input voltage at the input node. The transistor means is coupled to a settable current source which operates to control the effective value of the controllable effective resistance. The invention also includes a filter which employs the controllable effective resistance to vary the breakpoint frequency of the filter. Also, a phase-locked loop apparatus employing the filter is disclosed.

Abstract: In a water soluble glass composition for effecting cross-linking of a polycarboxylic acid cement, typically polyacrylic acid, the glass is treated with phosphorus pentoxide or a phosphate containing material. This inhibits the initial setting stage of the cement and thus prolongs the period within which the cement can be worked. The glass may be of the zinc oxide/boric oxide/alumina type or of the fluoroaluminoborosilicate type.