Patents by Inventor Neil R. McLellan

Neil R. McLellan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8847383
    Abstract: An integrated circuit package strip employs a stiffener layer that houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: September 30, 2014
    Assignee: ATI Technologies ULC
    Inventors: Neil R. McLellan, Vincent K. Chan, Roden R. Topacio, III
  • Patent number: 8564122
    Abstract: Various circuit boards and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an electrically non-functional component to a surface of a first circuit board. The electrically non-functional component has a first elevation. The surface of the circuit board is adapted to have a semiconductor chip mounted thereon. An electrically functional component is mounted to the surface inward from the electrically non-functional component. The electrically functional component has a second elevation less than the first elevation.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: October 22, 2013
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Neil R. McLellan, Liane Martinez, Yip Seng Low, Suming Hu
  • Publication number: 20130147012
    Abstract: Various circuit boards and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an electrically non-functional component to a surface of a first circuit board. The electrically non-functional component has a first elevation. The surface of the circuit board is adapted to have a semiconductor chip mounted thereon. An electrically functional component is mounted to the surface inward from the electrically non-functional component. The electrically functional component has a second elevation less than the first elevation.
    Type: Application
    Filed: December 9, 2011
    Publication date: June 13, 2013
    Inventors: Neil R. McLellan, Liane Martinez, Yip Seng Low, Suming Hu
  • Publication number: 20120127689
    Abstract: The present disclosure relates to an improved integrated circuit package and method with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.
    Type: Application
    Filed: February 1, 2012
    Publication date: May 24, 2012
    Applicant: ATI TECHNOLOGIES ULC
    Inventors: Neil R. McLellan, Vincent K. Chan, Roden R. Topacio
  • Patent number: 8120170
    Abstract: An integrated circuit package employs a stiffener layer that houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: February 21, 2012
    Assignee: ATI Technologies ULC
    Inventors: Neil R. McLellan, Vincent K. Chan, Roden R. Topacio
  • Publication number: 20080197477
    Abstract: The present disclosure relates to an improved integrated circuit package with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.
    Type: Application
    Filed: April 28, 2008
    Publication date: August 21, 2008
    Applicant: ATI Technologies Inc.
    Inventors: Neil R. McLellan, Vincent K. Chan, Roden R. Topacio
  • Publication number: 20080054490
    Abstract: The present disclosure relates to an improved integrated circuit package with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.
    Type: Application
    Filed: August 31, 2006
    Publication date: March 6, 2008
    Applicant: ATI Technologies Inc.
    Inventors: Neil R. McLellan, Vincent K. Chan, Roden R. Topacio
  • Patent number: 5130783
    Abstract: A thin film package is formed using a lost cost TAB interconnection on a semiconductor device and sandwiching the device between thin films of plastic to form a sealed, thin, light weight package for the semiconductor device.
    Type: Grant
    Filed: March 4, 1991
    Date of Patent: July 14, 1992
    Assignee: Texas Instruments Incorporated
    Inventor: Neil R. McLellan
  • Patent number: 4921550
    Abstract: A solder paste mixture for soldering surface mount devices to a circuit board using a reflow soldering process which utilizes a vapor phase furnace. The solder paste mixture has a metallic content which is 63% tin and 37% lead. The metallic content of the paste consists of 150 micron particles of 100% tin and 150 micron particles of an alloy of 10% tin and 90% lead. Included in the process of soldering components to the circuit board is the step of prebaking the circuit board with solder paste and components in their proper place on the board.
    Type: Grant
    Filed: July 21, 1989
    Date of Patent: May 1, 1990
    Assignee: Texas Instruments Incorporated
    Inventor: Neil R. McLellan
  • Patent number: 4865654
    Abstract: A solder paste mixture for soldering surface mount devices to a circuit board using a reflow soldering process which utilize a vapor phase furnace. The solder paste mixture has a metallic content which is 63% tin and 37% lead. The metallic content of the paste consists of 150 micron particles of 100% tin and 150 micron particles of an alloy of 10% tin and 90% lead. Included in the process of soldering components to the circuit board is the step of prebaking the circuit board with solder paste and components in their proper place on the board.
    Type: Grant
    Filed: December 17, 1987
    Date of Patent: September 12, 1989
    Assignee: Texas Instruments Incorporated
    Inventor: Neil R. McLellan
  • Patent number: 4767471
    Abstract: A solder paste mixture for soldering surface mount devices to a circuit board using a reflow soldering process which utilizes a vapor phase furnace. The solder paste mixture has a metallic content which is 63% tin and 37% lead. The metallic content of the paste consists of 150 micron particles of 100% tin and 150 micron particles of an alloy of 10% tin and 90% lead. Included in the process of soldering components to the circuit board is the step of prebaking the circuit board with solder paste and components in their proper place on the board.
    Type: Grant
    Filed: October 3, 1986
    Date of Patent: August 30, 1988
    Assignee: Texas Instruments Incorporated
    Inventor: Neil R. McLellan