Patents by Inventor Neil R. McLellan
Neil R. McLellan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8847383Abstract: An integrated circuit package strip employs a stiffener layer that houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.Type: GrantFiled: February 1, 2012Date of Patent: September 30, 2014Assignee: ATI Technologies ULCInventors: Neil R. McLellan, Vincent K. Chan, Roden R. Topacio, III
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Patent number: 8564122Abstract: Various circuit boards and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an electrically non-functional component to a surface of a first circuit board. The electrically non-functional component has a first elevation. The surface of the circuit board is adapted to have a semiconductor chip mounted thereon. An electrically functional component is mounted to the surface inward from the electrically non-functional component. The electrically functional component has a second elevation less than the first elevation.Type: GrantFiled: December 9, 2011Date of Patent: October 22, 2013Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Neil R. McLellan, Liane Martinez, Yip Seng Low, Suming Hu
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Publication number: 20130147012Abstract: Various circuit boards and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an electrically non-functional component to a surface of a first circuit board. The electrically non-functional component has a first elevation. The surface of the circuit board is adapted to have a semiconductor chip mounted thereon. An electrically functional component is mounted to the surface inward from the electrically non-functional component. The electrically functional component has a second elevation less than the first elevation.Type: ApplicationFiled: December 9, 2011Publication date: June 13, 2013Inventors: Neil R. McLellan, Liane Martinez, Yip Seng Low, Suming Hu
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Publication number: 20120127689Abstract: The present disclosure relates to an improved integrated circuit package and method with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.Type: ApplicationFiled: February 1, 2012Publication date: May 24, 2012Applicant: ATI TECHNOLOGIES ULCInventors: Neil R. McLellan, Vincent K. Chan, Roden R. Topacio
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Patent number: 8120170Abstract: An integrated circuit package employs a stiffener layer that houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.Type: GrantFiled: April 28, 2008Date of Patent: February 21, 2012Assignee: ATI Technologies ULCInventors: Neil R. McLellan, Vincent K. Chan, Roden R. Topacio
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Publication number: 20080197477Abstract: The present disclosure relates to an improved integrated circuit package with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.Type: ApplicationFiled: April 28, 2008Publication date: August 21, 2008Applicant: ATI Technologies Inc.Inventors: Neil R. McLellan, Vincent K. Chan, Roden R. Topacio
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Publication number: 20080054490Abstract: The present disclosure relates to an improved integrated circuit package with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.Type: ApplicationFiled: August 31, 2006Publication date: March 6, 2008Applicant: ATI Technologies Inc.Inventors: Neil R. McLellan, Vincent K. Chan, Roden R. Topacio
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Patent number: 5130783Abstract: A thin film package is formed using a lost cost TAB interconnection on a semiconductor device and sandwiching the device between thin films of plastic to form a sealed, thin, light weight package for the semiconductor device.Type: GrantFiled: March 4, 1991Date of Patent: July 14, 1992Assignee: Texas Instruments IncorporatedInventor: Neil R. McLellan
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Patent number: 4921550Abstract: A solder paste mixture for soldering surface mount devices to a circuit board using a reflow soldering process which utilizes a vapor phase furnace. The solder paste mixture has a metallic content which is 63% tin and 37% lead. The metallic content of the paste consists of 150 micron particles of 100% tin and 150 micron particles of an alloy of 10% tin and 90% lead. Included in the process of soldering components to the circuit board is the step of prebaking the circuit board with solder paste and components in their proper place on the board.Type: GrantFiled: July 21, 1989Date of Patent: May 1, 1990Assignee: Texas Instruments IncorporatedInventor: Neil R. McLellan
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Patent number: 4865654Abstract: A solder paste mixture for soldering surface mount devices to a circuit board using a reflow soldering process which utilize a vapor phase furnace. The solder paste mixture has a metallic content which is 63% tin and 37% lead. The metallic content of the paste consists of 150 micron particles of 100% tin and 150 micron particles of an alloy of 10% tin and 90% lead. Included in the process of soldering components to the circuit board is the step of prebaking the circuit board with solder paste and components in their proper place on the board.Type: GrantFiled: December 17, 1987Date of Patent: September 12, 1989Assignee: Texas Instruments IncorporatedInventor: Neil R. McLellan
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Patent number: 4767471Abstract: A solder paste mixture for soldering surface mount devices to a circuit board using a reflow soldering process which utilizes a vapor phase furnace. The solder paste mixture has a metallic content which is 63% tin and 37% lead. The metallic content of the paste consists of 150 micron particles of 100% tin and 150 micron particles of an alloy of 10% tin and 90% lead. Included in the process of soldering components to the circuit board is the step of prebaking the circuit board with solder paste and components in their proper place on the board.Type: GrantFiled: October 3, 1986Date of Patent: August 30, 1988Assignee: Texas Instruments IncorporatedInventor: Neil R. McLellan