Abstract: A method and system of controlling out of order execution pipelines using issue tags is disclosed. The issue tags are used to dynamically calculate pipeline skew parameters that track the relative position of a load/store instruction in a load/store pipeline and a simultaneously issued integer instruction in a variable length integer pipeline. The issue tags and pipeline skew parameters are used to improve data hazard detection, pipeline stalling, and instruction cancellation.

Abstract: A variable length instruction pipeline includes optional expansion stages that can be included in the variable length instruction pipeline to avoid pipeline stalls. The expansion stages are removed from the variable length instruction pipeline when not needed to reduce the length of the pipeline, which reduces latency and other problems associated with long pipelines. For example, in one embodiment of the present invention, a variable length instruction pipeline includes a first pipeline stage, a first expansion stage, and a second pipeline stage. The second pipeline stage is configured to selectively receive instructions from the first pipeline stage or the first expansion stage if the first expansion stage holds an instruction.

Abstract: A variable length instruction pipeline includes optional expansion stages that can be included in the variable length instruction pipeline to avoid pipeline stalls. The expansion stages are removed from the variable length instruction pipeline when not needed to reduce the length of the pipeline, which reduces latency and other problems associated with long pipelines. For example, in one embodiment of the present invention, a variable length instruction pipeline includes a first pipeline stage, a first expansion stage, and a second pipeline stage. The second pipeline stage is configured to selectively receive instructions from the first pipeline stage or the first expansion stage if the first expansion stage holds an instruction.

Abstract: A variable length instruction pipeline includes optional expansion stages that can be included in the variable length instruction pipeline to avoid pipeline stalls. The expansion stages are removed from the variable length instruction pipeline when not needed to reduce the length of the pipeline, which reduces latency and other problems associated with long pipelines. For example, in one embodiment of the present invention, a variable length instruction pipeline includes a first pipeline stage, a first expansion stage, and a second pipeline stage. The second pipeline stage is configured to selectively receive instructions from the first pipeline stage or the first expansion stage if the first expansion stage holds an instruction.

Abstract: A programmable logic cell suitable for use in a programmable gate array and able to produce any logical function of two inputs, operate as a 2 to 1 multiplexor or a data latch is formed by four multiplexors, five inverters and an OR gate to provide a very fast programmable logic cell.

Abstract: A programmable logic cell has two inputs and six outputs, each output being a different logical function of the inputs. Each output is generated by a pair of NMOS transistors, one transistor of each pair having its gate connected to one of the inputs and the other transistor of each pair having its gate connected to the inverse of the same input.

Abstract: A circuit arrangement comprising, for each bit location in a column of a RAM, an input shift register, a multiplexer and a comparator. The input data bit is stored in the shift register, and the multiplexer is arranged during a write cycle, to write the data bit into a bit position. During a verification cycle, the multiplexer is arranged to write the inverse data bit into the same position, and the comparator compares the output bit position of the RAM with the inverse data bit. The result is stored in the shift register, which can be down-loaded for analysis.