Abstract: A circuit having load jump mitigation, including: circuit processing stages arranged in a pipeline configuration and operable based on respective stage clock signals; and clock control circuits respectively connected to the circuit processing stages to control the respective stage clock signals.

Abstract: Handling an exception includes (i) executing a return from an exception; and (ii) executing a subsequent instruction with an additional functionality in case the additional functionality of the subsequent instruction can be triggered by a special instruction.

Abstract: A device includes an overlay mechanism, system with devices each including an overlay mechanism with an individually programmable delay or method for overlaying data. A method for overlaying data includes redirecting an access which is directed to a first memory location to a second memory location. The method for overlaying data selectively delays access to the second memory location in case of a redirection by a time.

Abstract: A device includes an overlay mechanism, system with devices each including an overlay mechanism with an individually programmable delay or method for overlaying data. A method for overlaying data includes redirecting an access which is directed to a first memory location to a second memory location. The method for overlaying data selectively delays access to the second memory location in case of a redirection by a time.

Abstract: A device includes an overlay mechanism, system with devices each including an overlay mechanism with an individually programmable delay or method for overlaying data. A method for overlaying data includes redirecting an access which is directed to a first memory location to a second memory location. The method for overlaying data selectively delays access to the second memory location in case of a redirection by a time.

Abstract: Handling an exception includes (i) executing a return from an exception; and (ii) executing a subsequent instruction with an additional functionality in case the additional functionality of the subsequent instruction can be triggered by a special instruction.

Abstract: A device includes an overlay mechanism, system with devices each including an overlay mechanism with an individually programmable delay or method for overlaying data. A method for overlaying data includes redirecting an access which is directed to a first memory location to a second memory location. The method for overlaying data selectively delays access to the second memory location in case of a redirection by a time.

Abstract: A system and method for signature-based redundancy comparison provides for receiving, by a master part, an input signal and generating, by the master part, a binary output signal, generating a delayed input signal based on the input signal, generating a first output signature based on the binary output signal, and generating a delayed first output signature based on the first output signature. The system and method further comprise generating a delayed binary output signal based on the delayed input signal, generating, by a checker part, a delayed second output signature based on the delayed binary output signal, comparing the delayed first output signature with the delayed second output signature, and generating an error signal, where the state of the error signal is based upon the comparison.

Abstract: A system and method for signature-based redundancy comparison provides for receiving, by a master part, an input signal and generating, by the master part, a binary output signal, generating a delayed input signal based on the input signal, generating a first output signature based on the binary output signal, and generating a delayed first output signature based on the first output signature. The system and method further comprise generating a delayed binary output signal based on the delayed input signal, generating, by a checker part, a delayed second output signature based on the delayed binary output signal, comparing the delayed first output signature with the delayed second output signature, and generating an error signal, where the state of the error signal is based upon the comparison.

Abstract: An electronic processing device has an integer pipeline and a load/store pipeline disposed in parallel to receive a series of instructions via a Fetch stage and a Predecode stage. If an instruction is stalled in a Decode stage of the integer pipeline, one or more Delay stages can be switched into and out of the integer pipeline between the Decode stage and the Predecode stage so as to increase or decrease its effective length. This allows the Predecode stage to continue to issue instructions and therefore the load/store pipeline does not need to stall. The maximum number of delay stages that need to be available for switching into the integer pipeline is the same as a load-use penalty for that pipeline.