Abstract: The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored in a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first date register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferrably stored in another data register.

Abstract: The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored In a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first data register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferably stored in another data register.

Abstract: The graphics processing apparatus of the present invention utilizes individual registers of a register file to store the X and Y coordinates of pixels. These X and Y coordinates though formed into a single data word are separable by, for example, having the most significant bits specifying the Y coordinate and the least significant bits specifying the Y coordinate. The graphics processing apparatus supports instructions which provide separate and independent data manipulation of these X and Y coordinates. These X Y coordinate manipulation instructions can provide for separate X Y arithmetic operations on two data words, separate X and Y compare operations, separate X and Y data move operations and a conversion between the X Y address form to the linear address form. This technique is highly useful for manipulation of X Y address coordinates in a visual display system employing bit mapped graphics.

Abstract: The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored in a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first date register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferrably stored in another data register.

Abstract: A microprocessor, specially adapted for graphics processing applications, and which has a self-emulation capability by which the contents of its internal registers may be dumped or loaded to or from external memory on an instruction-by-instruction basis, is disclosed. The microprocessor has circuitry which is responsive to an emulate enable signal, or to a predetermined instruction code, so that normal execution is halted at the end of the ion, with execution jumping to a predetermined vector. Responsive to a dump signal, the microprocessor begins execution of a routine which presents a predetermined series of memory addresses on a memory bus, in conjunction with the contents of registers internal to the microprocessor. Accordingly, the addressed locations of a memory device connected to the memory bus can be written with the register contents, for subsequent interrogation by the user.

Abstract: The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored in a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first date register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferrably stored in another data register.

Abstract: The graphics processing apparatus of the present invention utilizes individual registers of a register file to store the X and Y coordinates of pixels. These X and Y coordinates though formed into a single data word are separable by, for example, having the most significant bits specifying the Y coordinate and the least significant bits specifying the Y coordinate. The graphics processing apparatus supports instructions which provide separate and independent data manipulation of these X and Y coordinates. These X Y coordinate manipulation instructions can provide for separate X Y arithmetic operations on two data words, separate X and Y compare operations, separate X and Y data move operations and a conversion between the X Y address form to the linear address form. This technique is highly useful for manipulation of X Y address coordinates in a visual display system employing bit mapped graphics.

Abstract: A microprocessor, specially adapted for graphics processing applications, and which has a self-emulation capability by which the contents of its internal registers may be dumped or loaded to or from external memory on an instruction-by-instruction basis, is disclosed. The microprocessor has circuitry which is responsive to an emulate enable signal, or to a predetermined instruction code, so that normal execution is halted at the end of the ion, with execution jumping to a predetermined vector. Responsive to a dump signal, the microprocessor begins execution of a routine which presents a predetermined series of memory addresses on a memory bus, in conjunction with the contents of registers internal to the microprocessor. Accordingly, the addressed locations of a memory device connected to the memory bus can be written with the register contents, for subsequent interrogation by the user.