Patents by Inventor Neil Tracht

Neil Tracht has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060214238
    Abstract: Methods and apparatus are provided for RF switches (100, 200). In a preferred embodiment, the apparatus comprises one or more multi-gate n-channel enhancement mode FET transistors (50, 112, 114). When used in pairs (112, 114) each has its source (74, 133) coupled to a first common RF I/O port (116) and drains coupled respectively to second and third RF I/O ports (118, 120), and gates (136, 138), coupled respectively to first and second control terminals (122, 124). The multi-gate regions (66, 68) of the FETs (50) are parallel coupled, spaced-apart and serially arranged between source (72) and drain (76). Lightly doped n-regions (Ldd, Lds) are provided serially arranged between the spaced-apart multi-gate regions (66, 68), the lightly doped n-regions (Ldd, Lds) being separated by more heavily doped n-regions (84).
    Type: Application
    Filed: March 28, 2005
    Publication date: September 28, 2006
    Inventors: Elizabeth Glass, Olin Hartin, Neil Tracht
  • Publication number: 20060217078
    Abstract: Methods and apparatus are provided for RF switches (504, 612) integrated in a monolithic RF transceiver IC (500) and switched gain amplifier (600). Multi-gate n-channel enhancement mode FETs (50, 112, 114, Q1-3, Q4-6) are used with single gate FETs (150), resistors (Rb, Rg, Re, R1-R17) and capacitors (C1-C3) formed by the same manufacturing process. The multiple gates (68) of the FETs (50, 112, 114, Q1-3, Q4-6) are parallel coupled, spaced-apart and serially arranged between source (72) and drain (76). When used in pairs (112, 114) to form a switch (504) for a transceiver (500) each FET has its source (74) coupled to an antenna RF I/O port (116, 501) and drains coupled respectively to second and third RF I/O ports (118, 120; 507, 521) leading to the receiver side (530) or transmitter side (532) of the transceiver (500). The gates (136, 138) are coupled to control ports (122, 124; 503, 505; 606, 608).
    Type: Application
    Filed: March 28, 2005
    Publication date: September 28, 2006
    Inventors: Elizabeth Glass, Olin Hartin, Ngai Lau, Neil Tracht
  • Patent number: 5372967
    Abstract: A method of forming vertical trench inductor (10) includes providing a layer (11) and forming a plurality of trenches (12) vertically therein. The trenches (12) are filled with a conductive material (16) and etched using a photolithographically defined mask (17). The etching produces a conductive liner (18) covering two sidewalls (13) and a bottom surface (14) of the trench (12). A second conductive layer is formed and patterned to couple the conductive liner (18) covering a sidewall (13) of a first trench (12) to the conductive liner (18) of an opposite sidewall (13) of an adjacent trench (12) to form an inductive coil.
    Type: Grant
    Filed: May 2, 1994
    Date of Patent: December 13, 1994
    Assignee: Motorola, Inc.
    Inventors: Lalgudi M. G. Sundaram, Neil Tracht
  • Patent number: 5336921
    Abstract: A method of forming vertical trench inductor (10) includes providing a layer (11) and forming a plurality of trenches (12) vertically therein. The trenches (12) are filled with a conductive material (16) and etched using a photolithographically defined mask (17). The etching produces a conductive liner (18) covering two sidewalls (13) and a bottom surface (14) of the trench (12). A second conductive layer is formed and patterned to couple the conductive liner (18) covering a sidewall (13) of a first trench (12) to the conductive liner (18) of an opposite sidewall (13) of an adjacent trench (12) to form an inductive coil.
    Type: Grant
    Filed: January 27, 1992
    Date of Patent: August 9, 1994
    Assignee: Motorola, Inc.
    Inventors: Lalgudi M. G. Sundaram, Neil Tracht