Patents by Inventor NEIL ZHAO
NEIL ZHAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240103957Abstract: Apparatus, device, methods and system relating to a vehicular telemetry environment for the for identifying in real time unpredictable network communication faults based upon pre-processed raw telematics big data logs that may include GPS data and an indication of vehicle status data, and supplemental data that may further include location data and network data.Type: ApplicationFiled: August 3, 2023Publication date: March 28, 2024Applicant: Geotab Inc.Inventors: Neil Charles Cawse, Daniel Michael Dodgson, Yi Zhao
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Patent number: 9147749Abstract: A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate; and forming a trench in the semiconductor substrate by etching the semiconductor substrate. The methods also includes forming a threshold-adjusting layer doped with a certain type of threshold-adjusting ions to adjust the threshold voltage of the transistor on the semiconductor substrate in the trench; and forming a carrier drifting layer on the threshold-adjusting layer. Further the method includes forming a gate structure on the carrier drifting layer corresponding to the trench.Type: GrantFiled: September 10, 2013Date of Patent: September 29, 2015Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventor: Neil Zhao
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Patent number: 9112020Abstract: Various embodiments provide transistor devices and fabrication methods. An exemplary transistor device with improved carrier mobility can be formed by first forming a confining layer on a semiconductor substrate to confine impurity ions diffused from the semiconductor substrate to the confining layer. An epitaxial silicon layer can be formed on the confining layer, followed by forming a gate structure on the epitaxial silicon layer. A portion of the epitaxial silicon layer can be used as an intrinsic channel region. A source region and a drain region can be formed in portions of each of the epitaxial silicon layer, the confining layer, and the semiconductor substrate.Type: GrantFiled: January 28, 2015Date of Patent: August 18, 2015Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPInventors: Neil Zhao, Mieno Fumitake
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Publication number: 20150137146Abstract: Various embodiments provide transistor devices and fabrication methods. An exemplary transistor device with improved carrier mobility can be formed by first forming a confining layer on a semiconductor substrate to confine impurity ions diffused from the semiconductor substrate to the confining layer. An epitaxial silicon layer can be formed on the confining layer, followed by forming a gate structure on the epitaxial silicon layer. A portion of the epitaxial silicon layer can be used as an intrinsic channel region. A source region and a drain region can be formed in portions of each of the epitaxial silicon layer, the confining layer, and the semiconductor substrate.Type: ApplicationFiled: January 28, 2015Publication date: May 21, 2015Inventors: NEIL ZHAO, MIENO FUMITAKE
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Patent number: 8975642Abstract: Various embodiments provide transistor devices and fabrication methods. An exemplary transistor device with improved carrier mobility can be formed by first forming a confining layer on a semiconductor substrate to confine impurity ions diffused from the semiconductor substrate to the confining layer. An epitaxial silicon layer can be formed on the confining layer, followed by forming a gate structure on the epitaxial silicon layer. A portion of the epitaxial silicon layer can be used as an intrinsic channel region. A source region and a drain region can be formed in portions of each of the epitaxial silicon layer, the confining layer, and the semiconductor substrate.Type: GrantFiled: November 27, 2012Date of Patent: March 10, 2015Assignee: Semiconductor Manufacturing International CorpInventors: Neil Zhao, Mieno Fumitake
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Publication number: 20140319625Abstract: A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate; and forming a trench in the semiconductor substrate by etching the semiconductor substrate. The methods also includes forming a threshold-adjusting layer doped with a certain type of threshold-adjusting ions to adjust the threshold voltage of the transistor on the semiconductor substrate in the trench; and forming a carrier drifting layer on the threshold-adjusting layer. Further the method includes forming a gate structure on the carrier drifting layer corresponding to the trench.Type: ApplicationFiled: September 10, 2013Publication date: October 30, 2014Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventor: NEIL ZHAO
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Patent number: 8846527Abstract: A method is provided for fabricating an MOS transistor. The method includes providing a semiconductor substrate, and forming a gate structure having a gate dielectric layer and a gate metal layer on the semiconductor substrate. The method also includes forming offset sidewall spacers at both sides of the gate structure, and forming lightly doped regions in semiconductor substrate at both sides of the gate structure. Further, the method includes forming a first metal silicide region in each of the lightly doped regions, and forming main sidewall spacers at both sides of the gate structure. Further, the method includes forming heavily doped regions in semiconductor substrate at both sides of the gate structure and the main sidewall spacers, and forming a second metal silicide region in each of the heavily doped regions.Type: GrantFiled: May 6, 2013Date of Patent: September 30, 2014Assignee: Semiconductor Manufacturing International Corp.Inventor: Neil Zhao
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Publication number: 20140191316Abstract: A method is provided for fabricating an MOS transistor. The method includes providing a semiconductor substrate, and forming a gate structure having a gate dielectric layer and a gate metal layer on the semiconductor substrate. The method also includes forming offset sidewall spacers at both sides of the gate structure, and forming lightly doped regions in semiconductor substrate at both sides of the gate structure. Further, the method includes forming a first metal silicide region in each of the lightly doped regions, and forming main sidewall spacers at both sides of the gate structure. Further, the method includes forming heavily doped regions in semiconductor substrate at both sides of the gate structure and the main sidewall spacers, and forming a second metal silicide region in each of the heavily doped regions.Type: ApplicationFiled: May 6, 2013Publication date: July 10, 2014Applicant: Semiconductor Manufacturing International Corp.Inventor: NEIL ZHAO
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Publication number: 20140014968Abstract: Various embodiments provide transistor devices and fabrication methods. An exemplary transistor device with improved carrier mobility can be formed by first forming a confining layer on a semiconductor substrate to confine impurity ions diffused from the semiconductor substrate to the confining layer. An epitaxial silicon layer can be formed on the confining layer, followed by forming a gate structure on the epitaxial silicon layer. A portion of the epitaxial silicon layer can be used as an intrinsic channel region. A source region and a drain region can be formed in portions of each of the epitaxial silicon layer, the confining layer, and the semiconductor substrate.Type: ApplicationFiled: November 27, 2012Publication date: January 16, 2014Inventors: NEIL ZHAO, MIENO FUMITAKE