Abstract: In accordance with an embodiment, a linear voltage regulator includes: a first transistor coupled between a first input terminal and an output terminal, the first input terminal adapted to receive a first voltage, and the output terminal adapted to provide a regulated voltage; a second transistor coupled between a second input terminal and the output terminal, the second input terminal adapted to receive a second voltage; and an amplifier of a difference between a third voltage proportional to the voltage at the output terminal and a reference voltage, an output of said amplifier being selectively coupled to a control terminal of the first transistor and to a control terminal of the second transistor, the amplifier being supplied by a fourth voltage corresponding to a highest voltage of the first voltage and the second voltage.

Abstract: In accordance with an embodiment, a linear voltage regulator includes: a first transistor coupled between a first input terminal and an output terminal, the first input terminal adapted to receive a first voltage, and the output terminal adapted to provide a regulated voltage; a second transistor coupled between a second input terminal and the output terminal, the second input terminal adapted to receive a second voltage; and an amplifier of a difference between a third voltage proportional to the voltage at the output terminal and a reference voltage, an output of said amplifier being selectively coupled to a control terminal of the first transistor and to a control terminal of the second transistor, the amplifier being supplied by a fourth voltage corresponding to a highest voltage of the first voltage and the second voltage.

Abstract: A transponder communicates with a reader using active load modulation. The transponder includes a digital phase locked loop (DPLL), which, in operation, generates an active load modulation (ALM) carrier clock synchronized to carrier clock of the reader. Between transmission of data frames, the DPLL is placed in a lock mode of operation in which a feedback loop of the DPLL is closed. Within a transmitted data frame having a duration, the DPLL is placed, for the duration of the transmitted data frame, in a hold mode of operation in which the feedback loop is opened. A phase of the ALM carrier clock is adjusted at least once during the duration of the transmitted data frame.

Abstract: A transponder communicates with a reader using active load modulation. The transponder includes a digital phase locked loop (DPLL), which, in operation, generates an active load modulation (ALM) carrier clock synchronized to carrier clock of the reader. Between transmission of data frames, the DPLL is placed in a lock mode of operation in which a feedback loop of the DPLL is closed. Within a transmitted data frame having a duration, the DPLL is placed, for the duration of the transmitted data frame, in a hold mode of operation in which the feedback loop is opened. A phase of the ALM carrier clock is adjusted at least once during the duration of the transmitted data frame.

Abstract: A transponder communicates with a reader using active load modulation. The transponder includes a digital phase locked loop (DPLL), which, in operation, generates an active load modulation (ALM) carrier clock synchronized to carrier clock of the reader. Between transmission of data frames, the DPLL is placed in a lock mode of operation in which a feedback loop of the DPLL is closed. Within a transmitted data frame having a duration, the DPLL is placed, for the duration of the transmitted data frame, in a hold mode of operation in which the feedback loop is opened. A phase of the ALM carrier clock is adjusted at least once during the duration of the transmitted data frame.

Abstract: A transponder communicates with a reader using active load modulation. The transponder includes a digital phase locked loop (DPLL), which, in operation, generates an active load modulation (ALM) carrier clock synchronized to carrier clock of the reader. Between transmission of data frames, the DPLL is placed in a lock mode of operation in which a feedback loop of the DPLL is closed. Within a transmitted data frame having a duration, the DPLL is placed, for the duration of the transmitted data frame, in a hold mode of operation in which the feedback loop is opened. A phase of the ALM carrier clock is adjusted at least once during the duration of the transmitted data frame.