Abstract: A host computer with a FPGA is communicatively coupled to a configuration computer via a communication network. The host computer receives target configuration data from the configuration computer in encrypted form. A scanner module that is associated with the host computer decrypts the target configuration data and scans it for malicious code. The module writes the target configuration data to the fabric area of the FPGA and thereby configures the FPGA accordingly, to enable execution of a target array application. The scanner module is associated with the host computer by being implemented as trusted execution environment, or as an on-array-processor.

Abstract: A configurable hardware device comprises a configuration memory of a known total size, and a configurable fabric arranged for being configured according to information from the configuration memory and segmented in a static partition and at least one dynamic partition. A static partition is arranged for receiving a bit stream and a cryptographic nonce and comprises a read/write mechanism for interacting with the configuration memory. The received bit stream is stored in the configuration memory and used to configure an intended application in the dynamic partition. The static partition is arranged for computing, based on the cryptographic nonce, a checksum of the entire configuration memory and for outputting the checksum.

Abstract: A reconfigurable logic circuit comprises first, second and third switching circuits arranged for receiving first, second and third input bits, respectively, and each arranged for being configured in a mode wherein the corresponding input bit is passed on or in a mode; a first exclusive OR logic block operable on the outputs of the first, second and third switching circuits and arranged to output a sum bit; fourth, fifth and sixth switching circuits arranged for receiving a fourth, fifth and sixth input bits and arranged for being configured in a mode; first, second and third AND logic blocks, each arranged for receiving a different pair of the outputs of certain switching circuits; a second exclusive OR logic block operable on the outputs of certain AND logic blocks and arranged to produce a carry output bit.

Abstract: A configurable hardware device comprises a configuration memory of a known total size, and a configurable fabric arranged for being configured according to information from the configuration memory and segmented in a static partition and at least one dynamic partition. A static partition is arranged for receiving a bit stream and a cryptographic nonce and comprises a read/write mechanism for interacting with the configuration memory. The received bit stream is stored in the configuration memory and used to configure an intended application in the dynamic partition. The static partition is arranged for computing, based on the cryptographic nonce, a checksum of the entire configuration memory and for outputting the checksum.

Abstract: A reconfigurable logic circuit comprises first, second and third switching circuits arranged for receiving first, second and third input bits, respectively, and each arranged for being configured in a mode wherein the corresponding input bit is passed on or in a mode; a first exclusive OR logic block operable on the outputs of the first, second and third switching circuits and arranged to output a sum bit; fourth, fifth and sixth switching circuits arranged for receiving a fourth, fifth and sixth input bits and arranged for being configured in a mode; first, second and third AND logic blocks, each arranged for receiving a different pair of the outputs of certain switching circuits; a second exclusive OR logic block operable on the outputs of certain AND logic blocks and arranged to produce a carry output bit.