Abstract: A method is provided for synchronizing video data buffers in a system including: an encoder for encoding input data into a compressed data bitstream; an encoder buffer for storing the compressed data bitstream; a decoder buffer for receiving the compressed data bitstream, with a sum of an encoder buffer delay and a decoder buffer delay is constant; a variable rate transmission channel operatively connecting the encoder buffer and the decoder buffer; and a decoder for receiving and decoding the compressed data bitstream. The instantaneous encoder buffer delay is used to generate a control signal; the control signal is inserted into the compressed data bitstream following the encoder buffer. In an exemplary embodiment, each of the encoder and decoder performs encoding and decoding operations, respectively, in the Motion Picture Experts Group (MPEG) standard, using the VBV.sub.-- DLY parameter of the MPEG standard as the control signal.

Abstract: A system and method controls an encoder data buffer. The system includes an encoder for encoding input data as a first bit sequence in a bitstream; a processor having a predetermined size for converting the first bit sequence to a sequence having the predetermined size; and a decoder for decoding the modified bit sequence. The processor generates a set of modified bit sequences for facilitating editing thereof, in which the set of modified bit sequences, assembled in an arbitrary order, are decodeable by the decoder to generate a decoded output signal free of editing artifacts. The modified bit sequences are generated by inserting bits to the first bit sequence. The encoder encodes the input data at a rate such that a final capacity of the data buffer is less than a function of the predetermined size, a desired decoding rate, and an initial capacity of the encoder buffer. The data buffer has a total buffer capacity which is less than a function of the actual rate and the desired decoding rate.

Abstract: A video encoder control system and method are disclosed for controlling a video encoder using a processor having a multiple field delay circuit for delaying input video data by a predetermined number of frames, and a statistics generator for generating statistics from the video data to control the encoder. The statistics generator calculates a sum of absolute values of field differences between pixels, with the sum used for detecting a redundant field, for generating a film flag, and for controlling the encoder using the film flag. The statistics generator calculates averages of blocks of pixels, and a fade detector uses the averages for detecting fades between successive frames to generate a fade flag to control the encoding. The rate controller responds to the statistics to change the resolution of the encoding of successive frames. The processor outputs the film flags, scene change flags, and fade flags to the rate controller to control the encoding of the delayed video data.

Abstract: A temporally-pipelined predictive encoder/decoder circuit for encoding or decoding an input signal containing a sequence of data frames received at a particular frame rate and frame data rate into an output signal having an equal frame rate employs a plurality of N predictive encoders/decoders. An input buffer may be used to extract the information for each data frame in the input signal and supply such information to a corresponding one of the encoders/decoders at rate of 1/N of the particular frame data rate. Each encoder/decoder generates corresponding encoded/decoded information as it is received as well as provides digitized frame information to the encoder/decoder processing the next received image frame. The encoded/decoded information is provided to corresponding frame buffers which temporarily store such information.