Patents by Inventor Nelson Felix

Nelson Felix has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200292942
    Abstract: A method of making an adhesion layer of an extreme ultraviolet (EUV) stack is presented. The method includes grafting an ultraviolet (UV) sensitive polymer brush on a hardmask, the polymer brush including a UV cleavable unit, depositing EUV resist over the polymer brush, exposing the EUV resist to remove the EUV resist in exposed areas by applying a developer, and flooding the exposed area with a UV light and a solvent developer to remove exposed portions of the polymer brush.
    Type: Application
    Filed: March 12, 2019
    Publication date: September 17, 2020
    Inventors: Jing Guo, Bharat Kumar, Ekmini A. De Silva, Jennifer Church, Dario Goldfarb, Nelson Felix
  • Patent number: 10768532
    Abstract: A method of co-optimizing lithographic and etching processes for semiconductor fabrication. The method includes determining a first set of locations for a first complementary laser annealing to be performed on. The first complementary laser annealing is performed at the first set of locations on at least a first semiconductor wafer of a plurality of semiconductor wafers. The first complementary laser annealing is performed before or after a first post-exposure baking process for the at least first semiconductor wafer. After an etching process has been performed on at least the first semiconductor wafer, a second set of locations is determined for a second complementary laser annealing to be performed on. The second complementary laser annealing is performed at the second set of locations on at least a second semiconductor wafer of the plurality of semiconductor wafers. The second complementary laser annealing is performed before or after a second post-exposure baking process.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: September 8, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jing Sha, Ekmini Anuja De Silva, Nelson Felix, Derren Dunn
  • Publication number: 20200279956
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least a first channel region and a second channel region. The first channel region and the second channel region each include metal gate structures surrounding a different nanosheet channel layer. The metal gate structures of the first and second channel regions are respectively separated from each other by an unfilled gap. The method includes forming a gap fill layer between and in contact with gate structures surrounding nanosheet channel layers in multiple channel regions. Then, after the gap fill layer has been formed for each nanosheet stack, a masking layer is formed over the gate structures and the gap fill layer in at least a first channel region. The gate structures and the gap fill layer in at least a second channel region remain exposed.
    Type: Application
    Filed: May 19, 2020
    Publication date: September 3, 2020
    Inventors: Indira SESHADRI, Ekmini Anuja DE SILVA, Jing GUO, Ruqiang BAO, Muthumanickam SANKARAPANDIAN, Nelson FELIX
  • Publication number: 20200272045
    Abstract: Techniques for EUV resist pattern transfer using a graded hardmask are provided. In one aspect, a method of patterning is provided. The method includes: forming a graded hardmask on a device stack; depositing a resist onto the graded hardmask; patterning the resist to form a pattern in the resist having at least one feature; modifying at least one surface region to increase an etch rate of the graded hardmask; transferring the pattern from the resist to the graded hardmask; and transferring the pattern from the graded hardmask to at least one underlying layer of the device stack. A device structure formed by the patterning method is also provided.
    Type: Application
    Filed: February 21, 2019
    Publication date: August 27, 2020
    Inventors: Nelson Felix, Luciana Meli Thompson, Ashim Dutta, Ekmini A. De Silva
  • Patent number: 10755926
    Abstract: The invention herein includes enhancing the surface of an amorphous silicon hardmask through implantation of nonpolar, hydrophobic elements, resulting in increased hydrophobicity and increased resist adhesion of the amorphous silicon surface. According to the invention, implanting the hydrophobic elements may involve introduction of the hydrophobic elements into the surface of the amorphous silicon by way of low energy implantation and plasma treatment. The implanted hydrophobic element may be Boron, Xenon, Fluorine, Phosphorus, a combination thereof, or other hydrophobic elements. According to the invention, the surface of the amorphous silicon is enhanced with 10-15% hydrophobic element, however in other embodiments, this composition may be adjusted as needed. In any case, however, the invention herein includes maintaining an etch selectivity of the bulk amorphous silicon hardmask.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: August 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Abraham Arceo de la Pena, Ekmini Anuja De Silva, Nelson Felix
  • Patent number: 10755928
    Abstract: A plurality of mandrels and silicon dioxide spacer structures are formed, with the spacer structures interdigitated between the mandrels. An organic planarization layer is applied, as are a thin oxide layer and a layer of photoresist patterned in hole tone over the oxide layer, thereby defining a domain. At least one hole is etched in the thin oxide layer and the organic planarization layer to expose a portion of a hard mask layer surface between the spacer structures. A selective polymer brush is applied, which grafts only to the exposed hard mask surface, followed by solvent rinsing the domain to remove ungrafted polymer brush. At least one precursor is infused to an etch resistant material into the polymer brush by a sequential infiltration synthesis process. The organic planarization layer is ashed to convert the infused precursor into oxide form to further enhance etch selectivity to the hard mask layer.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: August 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chi-Chun Liu, Kristin Schmidt, Yann Mignot, Martha Inez Sanchez, Daniel Paul Sanders, Nelson Felix, Ekmini Anuja De Silva
  • Patent number: 10748823
    Abstract: An exemplary semiconductor wafer includes a lower sublayer of a first organic planarization layer (OPL) material; an upper sublayer of a second OPL material deposited onto the lower sublayer; and a detectable interface between the lower sublayer and the upper sublayer. The exemplary wafer is fabricated by depositing the lower sublayer; curing the lower sublayer; and after curing the lower sublayer, depositing the upper sublayer directly onto the lower sublayer.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: August 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yann Mignot, Alan Thomas, Daniel Sanders, Dario Goldfarb, Nelson Felix, Chi-Chun Liu, John Arnold
  • Patent number: 10741454
    Abstract: Methods are presented for forming multi-threshold field effect transistors. The methods generally include depositing and patterning an organic planarizing layer to protect underlying structures formed in a selected one of the nFET region and the pFET region of a semiconductor wafer. In the other one of the nFET region and the pFET region, structures are processed to form an undercut in the organic planarizing layer. The organic planarizing layer is subjected to a reflow process to fill the undercut. The methods are effective to protect a boundary between the nFET region and the pFET region.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jing Guo, Ekmini A. De Silva, Nicolas Loubet, Indira Seshadri, Nelson Felix
  • Publication number: 20200243335
    Abstract: A plurality of mandrels and silicon dioxide spacer structures are formed, with the spacer structures interdigitated between the mandrels. An organic planarization layer is applied, as are a thin oxide layer and a layer of photoresist patterned in hole tone over the oxide layer, thereby defining a domain. At least one hole is etched in the thin oxide layer and the organic planarization layer to expose a portion of a hard mask layer surface between the spacer structures. A selective polymer brush is applied, which grafts only to the exposed hard mask surface, followed by solvent rinsing the domain to remove ungrafted polymer brush. At least one precursor is infused to an etch resistant material into the polymer brush by a sequential infiltration synthesis process. The organic planarization layer is ashed to convert the infused precursor into oxide form to further enhance etch selectivity to the hard mask layer.
    Type: Application
    Filed: January 25, 2019
    Publication date: July 30, 2020
    Inventors: Chi-Chun Liu, Kristin Schmidt, Yann Mignot, Martha Inez Sanchez, Daniel Paul Sanders, Nelson Felix, Ekmini Anuja De Silva
  • Patent number: 10658521
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least a first channel region and a second channel region. The first channel region and the second channel region each include metal gate structures surrounding a different nanosheet channel layer. The metal gate structures of the first and second channel regions are respectively separated from each other by an unfilled gap. The method includes forming a gap fill layer between and in contact with gate structures surrounding nanosheet channel layers in multiple channel regions. Then, after the gap fill layer has been formed for each nanosheet stack, a masking layer is formed over the gate structures and the gap fill layer in at least a first channel region. The gate structures and the gap fill layer in at least a second channel region remain exposed.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Indira Seshadri, Ekmini Anuja De Silva, Jing Guo, Ruqiang Bao, Muthumanickam Sankarapandian, Nelson Felix
  • Patent number: 10656527
    Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate. Forming the patterning material film stack more particularly includes forming a hard mask layer and forming a resist layer over the hard mask layer. The hard mask layer is configured to support selective deposition of a metal-containing layer on the resist layer, the selective deposition of the metal-containing layer on the resist layer occurring after pattern development. The method further includes exposing the multi-layer patterning material film stack to patterning radiation to form a desired pattern in the resist layer, developing the pattern formed in the resist layer, and selectively depositing the metal-containing layer on the developed pattern in the resist layer. The selective deposition avoids deposition of the metal-containing layer on portions of the hard mask layer corresponding to respective openings in the resist layer.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ekmini Anuja De Silva, Indira Seshadri, Jing Guo, Ashim Dutta, Nelson Felix
  • Publication number: 20200135542
    Abstract: One or more embodiments described herein include systems, and/or methods that facilitate fabrication of a semiconductor device using a spacer lithography-etch process. According to an embodiment, a method can comprise performing a first lithography exposure and etch over a first layer of a semiconductor device, where the first lithography exposure and etch comprises forming one or more mandrels on a first region of a second layer by employing a first photoresist layer. The method can further comprise forming one or more spacers on a sidewall of the one or more mandrels and covering a second region of the second layer, where the second region is adjacent to the one or more mandrels. The method can further comprise forming a cut over a third region of the second layer and filling the third region with first material.
    Type: Application
    Filed: October 30, 2018
    Publication date: April 30, 2020
    Inventors: Nelson Felix, Ekmini Anuja De Silva, Luciana Meli Thompson, Yann Mignot
  • Publication number: 20200124972
    Abstract: A photolithography patterning stack and method for repairing defects in the stack. The stack includes an organic planarization layer, a hardmask layer, and a plurality of patterned photoresist lines in contact with the hardmask layer. A plurality of trenches is situated between the plurality of patterned photoresist lines. Each trench exposes a portion of the hardmask layer. A repairing layer is formed in contact with and only bonded to surfaces of the plurality of patterned photoresist lines. The method includes forming a photolithographic patterning stack. The stack includes at least a hardmask layer formed on one or more underlayers and a photoresist layer formed in contact with the hardmask layer. The photoresist layer is patterned into a plurality of patterned portions. A repairing layer is formed in contact with and only bonded to surfaces of each patterned portion of the plurality of portions.
    Type: Application
    Filed: October 23, 2018
    Publication date: April 23, 2020
    Inventors: Luciana MELI THOMPSON, Jing GUO, Nelson FELIX, Ekmini Anuja DE SILVA
  • Patent number: 10622248
    Abstract: A tunable amorphous silicon layer for use with multilayer patterning stacks can be used to maximize transparency and minimize reflections so as to improve overlay metrology contrast. By increasing the hydrogen content in the amorphous silicon layer, the extinction coefficient (k) value and the refractive index (n) value can be decreased to desired values. Methods for improving overlay metrology contrast with the tunable amorphous silicon layer are disclosed.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ekmini A. De Silva, Nelson Felix, Indira Seshadri, Stuart A. Sieg
  • Publication number: 20200105628
    Abstract: An exemplary semiconductor wafer includes a lower sublayer of a first organic planarization layer (OPL) material; an upper sublayer of a second OPL material deposited onto the lower sublayer; and a detectable interface between the lower sublayer and the upper sublayer. The exemplary wafer is fabricated by depositing the lower sublayer; curing the lower sublayer; and after curing the lower sublayer, depositing the upper sublayer directly onto the lower sublayer.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 2, 2020
    Inventors: Yann Mignot, Alan Thomas, Daniel Sanders, Dario Goldfarb, Nelson Felix, Chi-Chun Liu, John Arnold
  • Publication number: 20200090928
    Abstract: The invention herein includes enhancing the surface of an amorphous silicon hardmask through implantation of nonpolar, hydrophobic elements, resulting in increased hydrophobicity and increased resist adhesion of the amorphous silicon surface. According to the invention, implanting the hydrophobic elements may involve introduction of the hydrophobic elements into the surface of the amorphous silicon by way of low energy implantation and plasma treatment. The implanted hydrophobic element may be Boron, Xenon, Fluorine, Phosphorus, a combination thereof, or other hydrophobic elements. According to the invention, the surface of the amorphous silicon is enhanced with 10-15% hydrophobic element, however in other embodiments, this composition may be adjusted as needed. In any case, however, the invention herein includes maintaining an etch selectivity of the bulk amorphous silicon hardmask.
    Type: Application
    Filed: November 22, 2019
    Publication date: March 19, 2020
    Inventors: Abraham Arceo de la Pena, EKMINI ANUJA DE SILVA, NELSON FELIX
  • Patent number: 10586697
    Abstract: Embodiments of the present invention are directed to the wet stripping of an organic planarization layer (OPL) using reversible UV crosslinking and de-crosslinking. In a non-limiting embodiment of the invention, an interlayer dielectric is formed over a substrate. A trench is formed in the interlayer dielectric. A work function metal is formed over the interlayer dielectric such that a portion of the work function metal partially fills the trench. A UV sensitive OPL is formed over the work function metal such that a portion of the UV sensitive OPL fills the trench. The UV sensitive OPL can be crosslinked by applying light at a first UV frequency and de-crosslinked by applying light at a second UV frequency.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ekmini A. De Silva, Nelson Felix, Jing Guo, Indira Seshadri
  • Publication number: 20200070151
    Abstract: A microfluidic chip with a high volumetric flow rate is provided that includes at least two vertically stacked microfluidic channel layers, each microfluidic channel layer including an array of spaced apart pillars. Each microfluidic channel layer is interconnected by an inlet/outlet opening that extends through the microfluidic chip. The microfluidic chip is created without wafer to wafer bonding thus circumventing the cost and yield issues associated with microfluidic chips that are created by wafer bonding.
    Type: Application
    Filed: May 22, 2019
    Publication date: March 5, 2020
    Inventors: Chi-Chun Liu, Yann Mignot, Joshua T. Smith, Bassem M. Hamieh, Nelson Felix, Robert L. Bruce
  • Publication number: 20200070150
    Abstract: A microfluidic chip with high volumetric flow rate is provided that includes at least two vertically stacked microfluidic channel layers, each microfluidic channel layer including an array of spaced apart pillars. Each microfluidic channel layer is interconnected by an inlet/outlet opening that extends through the microfluidic chip. The microfluidic chip is created without wafer to wafer bonding thus circumventing the cost and yield issues associated with microfluidic chips that are created by wafer bonding.
    Type: Application
    Filed: May 22, 2019
    Publication date: March 5, 2020
    Inventors: Chi-Chun Liu, Yann Mignot, Joshua T. Smith, Bassem M. Hamieh, Nelson Felix, Robert L. Bruce
  • Patent number: 10578981
    Abstract: Methods for post-lithographic inspection using an e-beam inspection tool of organic extreme ultraviolet sensitive (EUV) sensitive photoresists generally includes conformal deposition of a removable metal carboxide or metal carboxynitride onto the relief image. The conformal deposition of the metal carboxide or metal carboxynitride includes a low temperature vapor deposition process of less than about 100° C. to provide a coating thickness of less than about 5 nanometers. Subsequent to e-beam inspection, the metal carboxide or metal carboxynitride coating is removed using a wet stripping process. Once stripped, the wafer can continue on to further process fabrication without being a sacrificial wafer.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Luciana Meli Thompson, Ekmini A. De Silva, Yasir Sulehria, Nelson Felix