Abstract: A search engine having a controller, a memory, and at least one hash-CAM (H-CAM). The memory includes a database of search values and associate content or just associate content. The controller uses search values to access the memory to obtain the search results. The H-CAM includes at least one set of paired hash units and CAM units and at least one logic unit. The CAM units hold values known to cause hash collisions in the paired hash units, and the logic unit prioritizes the hash and CAM unit outputs to address values usable to access the memory and obtain a search result at the controller that is not the result of a hash collision. The H-CAM may optionally include a search data storage to store the search values, so that they need not be stored in the memory, and a comparator to determine and handle new search data based hash collisions. The H-CAM may optionally also be cascaded.

Abstract: A content addressable memory (CAM) system includes CAM banks that can be linked together in a series to form a CAM module. Each CAM bank includes a CAM array with rows. In a lookup operation, each row asserts a field-match signal when a field from a key matches the field of a CAM entry held in the row. Each CAM bank receives a link-control signal, each received from the preceding CAM bank match-in signals for the rows, and each generates match-out signals for the rows. Some embodiments dynamically configure the CAM system into one or more independent CAM modules of various widths, according to data held in a configuration register or to the current value of the key or other search information. Some embodiments include multiple priority encoders that can be coupled to the match-out signals of dynamically selected CAM banks, thus advantageously allowing parallel lookup operations in the CAM modules.

Abstract: CAM devices that can be cascaded together to form CAM systems of different sizes are disclosed. The system has one or more clusters of M CAM devices, each device including (M?1) disable connections. Disable signals are used to avoid contention so that one CAM device generates the system output on a shared bus. To reduce pin count, the CAM device of priority N within each cluster has (N?1) of its disable connections programmed as inputs for disable-in signals received from higher-priority CAM devices, and its remaining (M?N) disable connections programmed as outputs for disable-out signals provided to lower-priority CAM devices. Some embodiments include two or more clusters of CAM devices and a controller. In some embodiments, the CAM system works as fast as a single CAM device. Some embodiments impose no architectural limits on the number of CAM devices that can be cascaded together.

Abstract: A search scheme (10) in which a controller (14) provides a search key (16) to a search engine (18, 36). In one variation, the search engine (18) provides a match address (20) based on prefix matching to an associate content (AC) memory (22) and the AC memory provides a search result (24) back to the controller. In an other variation the search engine (36) effectively may include the AC and itself provide the search result (24). Within the search engine (18, 36) every possible prefix for possible respective prefix lengths in the search key may be represented, either by a bit which addressable maps to the search result, by content addressable memory (CAM) (32) associatively mapping to the search result, or by directly addressing the search result (24).

Abstract: A relocation system to associatively search a database lookup table with a search key to addressably retrieve a corresponding associate content table record as a search result. The relocation system is implemented in search engine devices having associative memory (e.g., CAM) having one or more sections. The search engine devices employ relocation values when calculating addresses, one per section per device, with the relocation values optionally pre-calculated and stored in relocation registers. The search engine devices may be cascaded to construct a larger search engine. The search engine is typically used with a processor and addressable memory (e.g., RAM or ROM). In particular, the relocation system permits multiple databases to be concurrently stored and worked with in the associative and addressable memory.

Abstract: A search engine (100) having a controller (112), a memory (114), and a hash pointer unit (110). The memory (114) includes a database of search data and associate content, and the controller (112) uses individual search values to access the memory (114) to obtain individual search results. The controller (112) includes a hash function (116) that generates a hash value from a, typically large, search value into a, typically smaller, hash value that may be a hash collision. The controller (112) converts the hash value into a hash address which is communicated to the hash pointer unit (110), which receives the hash address and provides a hash pointer that is communicated to and used by the memory to look up respective search results. In this manner hash collisions are avoided and the size of the memory (114) is not a function of the degree of multi-way set-associativity used.

Abstract: A hash-CAM (H-CAM) which may work with a controller and a memory containing a database of either search values and associate content or associate content by itself The H-CAM includes at least one set of paired hash units and CAM units and at least one logic unit. The CAM units hold values known to cause hash collisions in the respectively paired hash units, and the logic unit prioritizes the hash and CAM unit outputs to a single address value usable to access the memory and obtain a search result at the controller that is not the result of a hash collision. The H-CAM may optionally include a search data storage to store the search values, so that they need not be stored in the memory, and a comparator to determine and handle newly determined hash collisions.

Abstract: A data distribution system suitable for use in a content addressable memory (CAM) search engine have a number of CAM units. A set of bank multiplexers each includes a set of multiplexing constructs that are controllable via respective bank control buses. Input data for storage in the CAM units as file data or for searching against pre-stored file data are provided to the bank multiplexers and the bank control buses direct the multiplexing constructs to selectively pass sub-portions of the input data onward to the CAM units thus distributing some or all of the input data to the CAM units, with the input data configurably ordered as desired, configurably duplicated as desired, or both. Optionally, a configuration register can hold multiple sets of programming data for loading onto the bank control buses to direct the multiplexing constructs, thus facilitating different distributions of the input data to the CAM units.

Abstract: CAM devices that can be cascaded together to form CAM systems of different sizes are disclosed. The system has one or more clusters of M CAM devices, each device including (M−1) disable connections. Disable signals are used to avoid contention so that one CAM device generates the system output on a shared bus. To reduce pin count, the CAM device of priority N within each cluster has (N−1) of its disable connections programmed as inputs for disable-in signals received from higher-priority CAM devices, and its remaining (M−N) disable connections programmed as outputs for disable-out signals provided to lower-priority CAM devices. Some embodiments include two or more clusters of CAM devices and a controller. In some embodiments, the CAM system works as fast as a single CAM device. Some embodiments impose no architectural limits on the number of CAM devices that can be cascaded together.

Abstract: A content addressable memory (CAM) system includes CAM banks that can be linked together in a series to form a CAM module. Each CAM bank includes a CAM array with rows. In a lookup operation, each row asserts a field-match signal when a field from a key matches the field of a CAM entry held in the row. Each CAM bank receives a link-control signal, each received from the preceding CAM bank match-in signals for the rows, and each generates match-out signals for the rows. Some embodiments dynamically configure the CAM system into one or more independent CAM modules of various widths, according to data held in a configuration register or to the current value of the key or other search information. Some embodiments include multiple priority encoders that can be coupled to the match-out signals of dynamically selected CAM banks, thus advantageously allowing parallel lookup operations in the CAM modules.

Abstract: A relocation system to associatively search a database lookup table with a search key to addressably retrieve a corresponding associate content table record as a search result. The relocation system is implemented in search engine devices having associative memory (e.g., CAM) having one or more sections. The search engine devices employ relocation values when calculating addresses, one per section per device, with the relocation values optionally pre-calculated and stored in relocation registers. The search engine devices may be cascaded to construct a larger search engine. The search engine is typically used with a processor and addressable memory (e.g., RAM or ROM). In particular, the relocation system permits multiple databases to be concurrently stored and worked with in the associative and addressable memory.

Abstract: A fast aging system (10) which may work with a memory (12) in which data words (16) having aging words (18) are stored. An aging address counter (20) selects an aging word (18) for updating based on a state change in a linear feedback shift register (LFSR) (24). Optionally, in the aging word (18) a zero value (52) may represent a permanent data words (16), a predefined non-zero value (56) may represent data words (16) which are available for replacement, and other zero values may represent data words (16) which are in various stages of valid lifetimes and which should not be replaced yet.

Abstract: A content addressable memory (CAM)(10, 102) and method having a data-in sub-circuit (44), memory cells (16, 18), a match-high line (36), a match-low line (38), and pre-charge devices (40, 42). Input lines (30, 32, 48, 50) from the data-in sub-circuit (44) are not necessarily discharged to ground in every cycle of a clock signal (62) used by the memory cells (16, 18). Further, the pre-charge devices (40, 42) may be operated at one half of the rate of the clock signal (62). Yet further, the CAM (10, 102) may be selectively configured to operate in either binary or ternary mode.

Abstract: A content addressable memory (CAM)(10, 102) and method having a data-in sub-circuit (44), memory cells (16, 18), a match-high line (36), a match-low line (38), and pre-charge devices (40, 42). Input lines (30, 32, 48, 50) from the data-in sub-circuit (44) are not necessarily discharged to ground in every cycle of a clock signal (62) used by the memory cells (16, 18). Further, the pre-charge devices (40, 42) may be operated at one half of the rate of the clock signal (62). Yet further, the CAM (10, 102) may be selectively configured to operate in either binary or ternary mode.

Abstract: A fast aging system (10) which may work with a memory (12) in which data words (16) having aging words (18) are stored. An aging address counter (20) selects an aging word (18) for updating based on a state change in a linear feedback shift register (LFSR) (24). Optionally, in the aging word (18) a zero value (52) may represent a permanent data words (16), a predefined non-zero value (56) may represent data words (16) which are available for replacement, and other zero values may represent data words (16) which are in various stages of valid lifetimes and which should not be replaced yet.

Abstract: A hash-CAM (H-CAM) which may work with a controller and a memory containing a database of either search values and associate content or associate content by itself The H-CAM includes at least one set of paired hash units and CAM units and at least one logic unit. The CAM units hold values known to cause hash collisions in the respectively paired hash units, and the logic unit prioritizes the hash and CAM unit outputs to a single address value usable to access the memory and obtain a search result at the controller that is not the result of a hash collision. The H-CAM may optionally include a search data storage to store the search values, so that they need not be stored in the memory, and a comparator to determine and handle newly determined hash collisions.

Abstract: A search engine having a controller, a memory, and at least one hash-CAM (H-CAM). The memory includes a database of search values and associate content or just associate content. The controller uses search values to access the memory to obtain the search results. The H-CAM includes at least one set of paired hash units and CAM units and at least one logic unit. The CAM units hold values known to cause hash collisions in the paired hash units, and the logic unit prioritizes the hash and CAM unit outputs to address values usable to access the memory and obtain a search result at the controller that is not the result of a hash collision. The H-CAM may optionally include a search data storage to store the search values, so that they need not be stored in the memory, and a comparator to determine and handle new search data based hash collisions. The H-CAM may optionally also be cascaded.

Abstract: A search engine (100) having a controller (112), a memory (114), and a hash pointer unit (110). The memory (114) includes a database of search data and associate content, and the controller (112) uses individual search values to access the memory (114) to obtain individual search results. The controller (112) includes a hash function (116) that generates a hash value from a, typically large, search value into a, typically smaller, hash value that may be a hash collision. The controller (112) converts the hash value into a hash address which is communicated to the hash pointer unit (110), which receives the hash address and provides a hash pointer that is communicated to and used by the memory to look up respective search results. In this manner hash collisions are avoided and the size of the memory (114) is not a function of the degree of multi-way set-associativity used.