Abstract: A system may include a first integrated circuit die comprising a first upper surface, an integrated circuit package substrate comprising a second upper surface, a wire coupled to the a first upper surface and to the second upper surface, a plurality of elements coupled to the first upper surface, and a second integrated circuit die coupled to the plurality of elements. A portion of the wire is disposed between the first integrated circuit die and the second integrated circuit die.

Abstract: A method, apparatus, and system relating to an IC package. The method includes providing a leadframe including a die pad for receiving a die and a plurality interconnect pillars, attaching a die to the die pad, bonding the die to the leadframe, and encapsulating the die and the leadframe to form a first IC package having a top surface and an opposing bottom surface, where the interconnect pillars extend from the top surface of the first IC package to the bottom surface of the first IC package.

Abstract: A system may include a first integrated circuit die comprising a first upper surface, an integrated circuit package substrate comprising a second upper surface, a wire coupled to the a first upper surface and to the second upper surface, a plurality of elements coupled to the first upper surface, and a second integrated circuit die coupled to the plurality of elements. A portion of the wire is disposed between the first integrated circuit die and the second integrated circuit die.

Abstract: In some embodiments, a substrate slot design for die stack packaging is presented. In this regard, an apparatus is introduced having a top integrated circuit die, a bottom integrated circuit die, and a substrate, including a slot through which the bottom integrated circuit die is wirebonded to contacts on a bottom surface of the substrate. Other embodiments are also disclosed and claimed.

Abstract: A system may include a first integrated circuit package including a first integrated circuit die and a first integrated circuit package substrate defining a first plurality of openings, a second integrated circuit package including a second integrated circuit die and a second integrated circuit package substrate defining a second plurality of openings, and a third substrate comprising a plurality of conductive projections. Each of the plurality of conductive projections may be disposed within a respective one of the first plurality of openings and a respective one of the second plurality of openings.

Abstract: The characteristics of a radio frequency package having short path length and the characteristics of a logic or memory package may be combined so that a high input/output connection is provided together with good radio frequency performance. In some embodiments, a non-radio frequency logic or memory die may be stacked on top of a larger radio frequency die. The radio frequency die may be connected to conventional quad flat no-lead lands. The non-radio frequency or logic or memory die may be connected to conventional leads. In some cases, some contacts on the radio frequency integrated circuit may be connected to leads as well, increasing the input/output capabilities of the radio frequency die.

Abstract: A method of fabricating a microelectronic multi-chip module comprises: providing a cavity down ball grid array having a die and solder balls on a die side thereof; providing a package including at least one die thereon on a die side thereof; stacking the package onto the backside of the ball grid array opposite from the die side of the ball grid array. The backsides of the ball grid array and of the package may include land pads for providing interconnection between the ball grid array and the package during stacking.

Abstract: A method and apparatus for multi-chip packages that are closely coupled using an interposer is disclosed. A top single chip or multi-chip encapsulated package with bottom side contacts is formed and tested. A bottom single chip or multi-chip package substrate having bottom contacts is formed. Then a hollow center interposer is connected to the periphery of the package substrate leaving the chips at the center exposed, and the hollow region is filled with an encapsulant to the level of the top of the interposer, to form the finished package having contact on the bottom and on the top. After the bottom package undergoes electrical function testing, the top package is soldered to the interposer forming a completed multi-chip package.