Patents by Inventor Nelson S. Xu

Nelson S. Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5619715
    Abstract: A data processor processes data strings from memory where the data strings do not begin or end at a memory boundary. A string is defined in memory by a starting address, a byte count defining the total number of bytes in the string, and a byte offset defining the position of the first byte in the starting address location. The processor stores the byte count and decrements the byte count as each multi-byte word is processed. A byte count mask circuit generates a byte count mask which has all 1s for each byte count greater than the number of bytes per memory word. When the number of bytes remaining to be processed is below the number of bytes in a memory word, the byte count mask generates 1s only for the positions corresponding to the positions of bytes of the string in the last memory word. An offset register stores the offset defining the position of the first byte in the first memory word of the string.
    Type: Grant
    Filed: May 25, 1995
    Date of Patent: April 8, 1997
    Assignee: International Business Machines Corporation
    Inventors: Robert M. Dinkjian, Lisa C. Heller, Steven R. Kordus, Kenneth A. Lauricella, Thomas W. Seigendall, Robert A. Skaggs, Nelson S. Xu
  • Patent number: 5608887
    Abstract: A data processor processes data strings from memory where the data strings do not begin or end at a memory boundary. A string is defined in memory by a starting address, a byte count defining the total number of bytes in the string, and a byte offset defining the position of the first byte in the starting address location. The processor stores the byte count and decrements the byte count as each multi-byte word is processed. A byte count mask circuit generates a byte count mask which has all 1s for each byte count greater than the number of bytes per memory word. When the number of bytes remaining to be processed is below the number of bytes in a memory word, the byte count mask generates 1s only for the positions corresponding to the positions of bytes of the string in the last memory word. An offset register stores the offset defining the position of the first byte in the first memory word of the string.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: March 4, 1997
    Assignee: International Business Machines Corporation
    Inventors: Robert M. Dinkjian, Lisa C. Heller, Steven R. Kordus, Kenneth A. Lauricella, Thomas W. Seigendall, Robert A. Skaggs, Nelson S. Xu
  • Patent number: 5465374
    Abstract: A data processor processes data strings from memory where the data strings do not begin or end at a memory boundary. A string is defined in memory by a starting address, a byte count defining the total number of bytes in the string, and a byte offset defining the position of the first byte in the starting address location. The processor stores the byte count and decrements the byte count as each multi-byte word is processed. A byte count mask circuit generates a byte count mask which has all 1s for each byte count greater than the number of bytes per memory word. When the number of bytes remaining to be processed is below the number of bytes in a memory word, the byte count mask generates 1s only for the positions corresponding to the positions of bytes of the string in the last memory word. An offset register stores the offset defining the position of the first byte in the first memory word of the string.
    Type: Grant
    Filed: January 12, 1993
    Date of Patent: November 7, 1995
    Assignee: International Business Machines Corporation
    Inventors: Robert M. Dinkjian, Lisa C. Heller, Steven R. Kordus, Kenneth A. Lauricella, Thomas W. Seigendall, Robert A. Skaggs, Nelson S. Xu
  • Patent number: 5253195
    Abstract: A high speed digital multiplier utilizes a variation in known shift-and-add algorithms. Each cycle, a single digit of the multiplier and the entire multiplicand are processed to form a "partial product" that is added to the result of the next cycle. The end result is a two part product, the high order product being generated by a carry-propagate adder, and the low order product being generated by a "spill adder" that produces one digit each cycle. Inputs of a carry-propagate adder are fed directly from outputs of a carry-save adder rather than running sum and carry registers. With a multiplier digit of 16-bits, a fixed point halfword multiply requires one execution cycle, a fixed point fullword multiply requires two execution cycles, and a floating point long multiply requires four execution cycles with additional overhead if pre- or post-normalization is required.
    Type: Grant
    Filed: February 4, 1993
    Date of Patent: October 12, 1993
    Assignee: International Business Machines Corporation
    Inventors: Harold J. Broker, Russell S. Cook, James O'Connor, Nelson S. Xu