Abstract: An apparatus and method for aligning a mask and wafer in the fabrication of ntegrated circuits utilizing alignment patterns on the mask and wafer. Each alignment pattern comprises a plurality of parallel alignment marks which are spaced from one another such that the patterns may be superimposed so that the marks of one pattern are positioned between marks of the other pattern. When the patterns are misaligned, a moire pattern is produced which disappears on alignment. The marks of each pattern are also disparately spaced from one another, permitting a gross to fine alignment. In aligning the patterns, each mark of one pattern is positioned between pairs of marks of the other pattern in an order corresponding to the widths of spaces defined between marks of the other pattern, progressing from the largest space width, giving gross alignment, to the smallest, giving fine alignment.