Patents by Inventor Nelson Wu
Nelson Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240028518Abstract: A processor includes a load and store unit (LSU) and a cache memory, and transfers data information from a store queue in the LSU to the cache memory. The cache memory requests an information packet from the LSU when the cache memory determines that an available entry exists in a store queue within the cache memory. The LSU acknowledges the request and transfers an information packet to the cache memory. The LSU anticipates that an additional available entry exists in the cache memory, transmits an additional acknowledgement to the cache memory, and transfers an additional information packet, before receiving an additional request from the cache memory. The cache memory stores the additional information packet if an additional available entry exists in the cache store queue. The cache memory rejects the additional information packet if no additional available entries exist in the cache store queue.Type: ApplicationFiled: July 21, 2022Publication date: January 25, 2024Inventors: Shakti Kapoor, Nelson Wu, Manoj Dusanapudi
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Publication number: 20230195649Abstract: Systems and methods for invalidating page translation entries are described. A processing element may apply a delay to a drain cycle of a store reorder queue (SRQ) of a processing element. The processing element may drain the SRQ under the delayed drain cycle. The processing element may receive a translation lookaside buffer invalidation (TLBI) instruction from an interconnect connecting the plurality of processing elements. The TLBI instruction may be an instruction to invalidate a translation lookaside buffer (TLB) entry corresponding to at least one of a virtual memory page and a physical memory frame. The TLBI instruction may be broadcasted by another processing element. The application of the delay to the drain cycle of the SRQ may decrease a difference between the drain cycle of the SRQ and an invalidation cycle associated with the TLBI.Type: ApplicationFiled: February 23, 2023Publication date: June 22, 2023Inventors: Shakti Kapoor, Nelson Wu, Manoj Dusanapudi
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Publication number: 20230195981Abstract: A system, mechanism, tool, programming product, processor, and/or method for generating a hazard in a processor includes: identifying one or more cache lines to invalidate in a second level memory of a processing core in the processor; invalidating, in response to identifying one or more cache lines to invalidate in the second level cache, the one or more identified cache lines in the second level memory; and invalidating, in response to invalidating the one or more identified cache lines in the second level memory, the corresponding one or more cache lines in a first level memory. In an aspect the hazard generating mechanism is triggered, preferably on demand, and includes in an approach searching for cache lines in the second level memory that are also in the first level memory.Type: ApplicationFiled: December 17, 2021Publication date: June 22, 2023Inventors: Shakti Kapoor, Nelson Wu, Manoj Dusanapudi
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Publication number: 20230122466Abstract: Methods and systems for validating cache coherence in a data processing system are described. A processing element may detect a load instruction requesting the processing element to transfer data from a global memory location to a local memory location. The processing element may apply, in response to detecting the load instruction requesting the processing element to transfer data from the global memory location to the local memory location, a delay to the transfer of the data from the global memory location to the local memory location. The processing element may execute the load instruction and transferring the data from the global memory location to the local memory location with the applied delay. The processing element may validate, in response to executing the load instruction and transferring the data with the applied delay, a cache coherence of the data processing system.Type: ApplicationFiled: October 20, 2021Publication date: April 20, 2023Inventors: Shakti Kapoor, Manoj Dusanapudi, Nelson Wu
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Publication number: 20230105945Abstract: Systems and methods for invalidating page translation entries are described. A processing element may apply a delay to a drain cycle of a store reorder queue (SRQ) of a processing element. The processing element may drain the SRQ under the delayed drain cycle. The processing element may receive a translation lookaside buffer invalidation (TLBI) instruction from an interconnect connecting the plurality of processing elements. The TLBI instruction may be an instruction to invalidate a translation lookaside buffer (TLB) entry corresponding to at least one of a virtual memory page and a physical memory frame. The TLBI instruction may be broadcasted by another processing element. The application of the delay to the drain cycle of the SRQ may decrease a difference between the drain cycle of the SRQ and an invalidation cycle associated with the TLBI.Type: ApplicationFiled: October 4, 2021Publication date: April 6, 2023Inventors: Shakti Kapoor, Nelson Wu, Manoj Dusanapudi
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Patent number: 11620235Abstract: Systems and methods for invalidating page translation entries are described. A processing element may apply a delay to a drain cycle of a store reorder queue (SRQ) of a processing element. The processing element may drain the SRQ under the delayed drain cycle. The processing element may receive a translation lookaside buffer invalidation (TLBI) instruction from an interconnect connecting the plurality of processing elements. The TLBI instruction may be an instruction to invalidate a translation lookaside buffer (TLB) entry corresponding to at least one of a virtual memory page and a physical memory frame. The TLBI instruction may be broadcasted by another processing element. The application of the delay to the drain cycle of the SRQ may decrease a difference between the drain cycle of the SRQ and an invalidation cycle associated with the TLBI.Type: GrantFiled: October 4, 2021Date of Patent: April 4, 2023Assignee: International Business Machines CorporationInventors: Shakti Kapoor, Nelson Wu, Manoj Dusanapudi
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Patent number: 11501046Abstract: A system is provided to validate a computer processor. The system includes a computing system configured to obtain core dump data including executable instructions corresponding to a code stored in a legacy processor. An instruction-level simulator is installed in the computing system and is configured to simulate the executable instructions to generate a plurality of instruction traces. The system further includes a pre-silicon chip model simulator configured to execute the instruction traces to generate performance data. The computer processor is verified based at least in part on the performance data.Type: GrantFiled: March 24, 2020Date of Patent: November 15, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nelson Wu, Daniel Isaac Rodriguez, Miguel Gomez Gonzalez, Shakti Kapoor
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Publication number: 20210303766Abstract: A system is provided to validate a computer processor. The system includes a computing system configured to obtain core dump data including executable instructions corresponding to a code stored in a legacy processor. An instruction-level simulator is installed in the computing system and is configured to simulate the executable instructions to generate a plurality of instruction traces. The system further includes a pre-silicon chip model simulator configured to execute the instruction traces to generate performance data. The computer processor is verified based at least in part on the performance data.Type: ApplicationFiled: March 24, 2020Publication date: September 30, 2021Inventors: Nelson Wu, Daniel Isaac Rodriguez, Miguel Gomez Gonzalez, Shakti Kapoor
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Patent number: 11094391Abstract: A processor memory is stress tested with a variable list insertion depth using list insertion test segments with non-naturally aligned data boundaries. List insertion test segments are interspersed into test code of a processor memory tests to change the list insertion depth without changing results of the test code. The list insertion test segments are the same structure as the segments of the test code and have non-naturally aligned boundaries. The list insertion test segments include list insertion segments and load/store segments. The list insertion segments locate a current memory location using a fixed segment at a known location. The load/store segments load and store list elements in memory.Type: GrantFiled: June 6, 2019Date of Patent: August 17, 2021Assignee: International Business Machines CorporationInventors: Manoj Dusanapudi, Shakti Kapoor, Nelson Wu
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Patent number: 11061821Abstract: Disclosed is a system, method and/or computer product that includes generating translation requests that are identical but have different expected results, transmitting the translation requests from a MMU tester to a non-core MMU disposed on a processor chip, where the non-core MMU is external to a processing core of the processor chip, and where the MMU tester is disposed on a computing component external to the processor chip. The method also includes receiving memory translation results from the non-core MMU at the MMU tester, comparing the results to determine if there is a flaw in the non-core MMU.Type: GrantFiled: November 25, 2019Date of Patent: July 13, 2021Assignee: International Business Machines CorporationInventors: Manoj Dusanapudi, Shakti Kapoor, Nelson Wu
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Patent number: 10748637Abstract: A system comprising a computer processor comprising a plurality of registers, a load-store unit configured to load data in at least one of the plurality of registers, and a memory. The memory includes a memory location mapped to a first virtual memory address and a second virtual memory address. Issuance of a load from the memory location via the first virtual memory address causes execution of a side effect. The memory also includes a computer program containing programming instructions that, when executed by the computer processor, performs an operation that includes storing a predetermined data value at the memory location, and testing the memory for errors during load operations.Type: GrantFiled: July 26, 2018Date of Patent: August 18, 2020Assignee: International Business Machines CorporationInventors: Nelson Wu, Manoj Dusanapudi, Shakti Kapoor, Nandhini Rajaiah
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Publication number: 20200089621Abstract: Disclosed is a system, method and/or computer product that includes generating translation requests that are identical but have different expected results, transmitting the translation requests from a MMU tester to a non-core MMU disposed on a processor chip, where the non-core MMU is external to a processing core of the processor chip, and where the MMU tester is disposed on a computing component external to the processor chip. The method also includes receiving memory translation results from the non-core MMU at the MMU tester, comparing the results to determine if there is a flaw in the non-core MMU.Type: ApplicationFiled: November 25, 2019Publication date: March 19, 2020Inventors: Manoj Dusanapudi, Shakti Kapoor, Nelson Wu
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Publication number: 20200035319Abstract: A system comprising a computer processor comprising a plurality of registers, a load-store unit configured to load data in at least one of the plurality of registers, and a memory. The memory includes a memory location mapped to a first virtual memory address and a second virtual memory address. Issuance of a load from the memory location via the first virtual memory address causes execution of a side effect. The memory also includes a computer program containing programming instructions that, when executed by the computer processor, performs an operation that includes storing a predetermined data value at the memory location, and testing the memory for errors during load operations.Type: ApplicationFiled: July 26, 2018Publication date: January 30, 2020Inventors: Nelson Wu, Manoj Dusanapudi, Shakti Kapoor, Nandhini Rajaiah
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Patent number: 10521355Abstract: Disclosed is a system, method and/or computer product that includes generating translation requests that are identical but have different expected results, transmitting the translation requests from a MMU tester to a non-core MMU disposed on a processor chip, where the non-core MMU is external to a processing core of the processor chip, and where the MMU tester is disposed on a computing component external to the processor chip. The method also includes receiving memory translation results from the non-core MMU at the MMU tester, comparing the results to determine if there is a flaw in the non-core MMU.Type: GrantFiled: December 15, 2017Date of Patent: December 31, 2019Assignee: International Business Machines CorporationInventors: Manoj Dusanapudi, Shakti Kapoor, Nelson Wu
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Patent number: 10489261Abstract: A circuit and method provide efficient stress testing of address translations in an integrated circuit such as a link processing unit. A random DMA mode (RDM) circuit provides a random input to index into a translation validation table (TVT) that is used to generate the real memory address. The RDM circuit allows testing all entries of the TVT, and thus all DMA modes, regardless of what bus agents are connected to the link processing unit. The RDM circuit may use a multiplexer to select between a runtime input and a random test input provided by the random bit generator. When the link processing unit is in a test mode a mode selection bit is asserted to select the random test input.Type: GrantFiled: September 28, 2018Date of Patent: November 26, 2019Assignee: International Business Machines CorporationInventors: Manoj Dusanapudi, Shakti Kapoor, Nelson Wu
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Patent number: 10481991Abstract: A circuit and method provide efficient stress testing of address translations in an integrated circuit such as a link processing unit. A random DMA mode (RDM) circuit provides a random input to index into a translation validation table (TVT) that is used to generate the real memory address. The RDM circuit allows testing all entries of the TVT, and thus all DMA modes, regardless of what bus agents are connected to the link processing unit. The RDM circuit may use a multiplexer to select between a runtime input and a random test input provided by the random bit generator. When the link processing unit is in a test mode a mode selection bit is asserted to select the random test input.Type: GrantFiled: September 26, 2018Date of Patent: November 19, 2019Assignee: International Business Machines CorporationInventors: Manoj Dusanapudi, Shakti Kapoor, Nelson Wu
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Patent number: 10438682Abstract: A processor memory is stress tested with a variable list insertion depth using list insertion test segments with non-naturally aligned data boundaries. List insertion test segments are interspersed into test code of a processor memory tests to change the list insertion depth without changing results of the test code. The list insertion test segments are the same structure as the segments of the test code and have non-naturally aligned boundaries. The list insertion test segments include list insertion segments and load/store segments. The list insertion segments locate a current memory location using a fixed segment at a known location. The load/store segments load and store list elements in memory.Type: GrantFiled: December 21, 2017Date of Patent: October 8, 2019Assignee: International Business Machines CorporationInventors: Manoj Dusanapudi, Shakti Kapoor, Nelson Wu
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Publication number: 20190287639Abstract: A processor memory is stress tested with a variable list insertion depth using list insertion test segments with non-naturally aligned data boundaries. List insertion test segments are interspersed into test code of a processor memory tests to change the list insertion depth without changing results of the test code. The list insertion test segments are the same structure as the segments of the test code and have non-naturally aligned boundaries. The list insertion test segments include list insertion segments and load/store segments. The list insertion segments locate a current memory location using a fixed segment at a known location. The load/store segments load and store list elements in memory.Type: ApplicationFiled: June 6, 2019Publication date: September 19, 2019Inventors: Manoj Dusanapudi, Shakti Kapoor, Nelson Wu
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Publication number: 20190198132Abstract: A processor memory is stress tested with a variable list insertion depth using list insertion test segments with non-naturally aligned data boundaries. List insertion test segments are interspersed into test code of a processor memory tests to change the list insertion depth without changing results of the test code. The list insertion test segments are the same structure as the segments of the test code and have non-naturally aligned boundaries. The list insertion test segments include list insertion segments and load/store segments. The list insertion segments locate a current memory location using a fixed segment at a known location. The load/store segments load and store list elements in memory.Type: ApplicationFiled: December 21, 2017Publication date: June 27, 2019Inventors: Manoj Dusanapudi, Shakti Kapoor, Nelson Wu
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Publication number: 20190188146Abstract: Disclosed is a system, method and/or computer product that includes generating translation requests that are identical but have different expected results, transmitting the translation requests from a MMU tester to a non-core MMU disposed on a processor chip, where the non-core MMU is external to a processing core of the processor chip, and where the MMU tester is disposed on a computing component external to the processor chip. The method also includes receiving memory translation results from the non-core MMU at the MMU tester, comparing the results to determine if there is a flaw in the non-core MMU.Type: ApplicationFiled: December 15, 2017Publication date: June 20, 2019Inventors: Manoj Dusanapudi, Shakti Kapoor, Nelson Wu