Abstract: In general, techniques are described for fused filament fabrication of abradable coatings. An additive manufacturing system comprising a substrate defining a major surface, a filament delivery device, and a computing device may be configured to perform various aspects of the techniques. The computing device may be configured to control the filament delivery device to deposit a filament on the substrate, the filament including a powder and a binder, wherein the binder is configured to be substantially removed from the filament and the powder includes a metal or alloy configured to be sintered to form an abradable layer.

Abstract: A Flash memory controller for a system having first and second microcontrollers configured to perform first and second functions, and further having a Flash memory medium shared by the two microcontrollers, includes first and second execute-in-place cache controllers respectively configured to cache program code retrieved from the Flash memory for execution by the respective microcontrollers. A cache-miss arbiter controls access by the microcontrollers to the Flash memory on occurrence of a cache miss in one of the cache controllers. The arbiter may allow aborting of a first fetching operation on behalf of one of the microcontrollers upon receipt of a fetch request from the other microcontroller if the first fetching operation has retrieved a desired data unit and a threshold amount of data. The Flash memory controller may also include a decryption engine configured to decrypt encrypted program code. The decryption mode is determined from address ranges.

Abstract: A Flash memory controller for a system having first and second microcontrollers configured to perform first and second functions, and further having a Flash memory medium shared by the two microcontrollers, includes first and second execute-in-place cache controllers respectively configured to cache program code retrieved from the Flash memory for execution by the respective microcontrollers. A cache-miss arbiter controls access by the microcontrollers to the Flash memory on occurrence of a cache miss in one of the cache controllers. The arbiter may allow aborting of a first fetching operation on behalf of one of the microcontrollers upon receipt of a fetch request from the other microcontroller if the first fetching operation has retrieved a desired data unit and a threshold amount of data. The Flash memory controller may also include a decryption engine configured to decrypt encrypted program code. The decryption mode is determined from address ranges.

Abstract: A network device including first, second and third transceiver modules, which transmit or receive first, second and third data signals. A control module generates a mask signal based on a parameter of the first, second or third transceiver modules. The mask signal includes a direction bit and a first channel that identifies a first frequency. The direction bit indicates a range of frequencies. Transmission on the first frequency and some of the range of frequencies causes desensitization of the second data signal. A hopping module, based on a clock signal, selects a second channel for the third data signal. An output module, based on the mask signal and the second channel, generates an overlap signal indicating whether potential desensitization of the first or third data signal exists. An arbitration module, based on the overlap signal, provides the first or third transceiver module access to a first or second switch module.

Abstract: Systems and techniques relating to wireless communications are described. A described technique includes performing, at a wireless communication device, an arbitration among multiple different wireless radio technologies, which collectively use two or more radio resources of the wireless communication device, to produce an arbitration result; and operating the two or more radio resources in accordance with the arbitration result. Performing the arbitration can include performing a first level arbitration between a request associated with a first technology of the multiple different wireless radio technologies and a request associated with a second technology of the multiple different wireless radio technologies to produce a first level result; and performing a second level arbitration to produce a second level result when indicated by the first level result. The arbitration result can be based on the first level result and the second level result, if any.

Abstract: A coexistence system including first and second transceiver modules and an arbitration module. The first transceiver module generates a first request signal and operates according to a first wireless communication standard. The first request signal requests transmission or reception for the first transceiver module. The second transceiver module generates a second request signal and an overlap signal and operates according to a second wireless communication standard. The second request signal requests permission for the second transceiver module to transmit or receive. The overlap signal indicates whether desensitization is expected of a frequency of the first transceiver module or a frequency of the second transceiver module. The arbitration module (i) based on the overlap signal, arbitrates the first and second request signals, and (ii) based on the arbitration of the first and second request signals, selectively connect antennas to the first and second transceiver modules in one multiple configurations.

Abstract: A decoding unit for decoding a modulated signal includes a summing unit having i) a first input, ii) a second input, and iii) an output. The summing unit is configured to i) receive the modulated signal at the first input, ii) receive a feedback signal at the second input, and iii) output a first waveform based on the modulated signal and the feedback signal. A demodulation unit has a first demodulation pathway and a second demodulation pathway. The demodulation unit is configured to i) select between the first demodulation pathway and the second demodulation pathway, ii) receive and demodulate the modulated signal with the first demodulation pathway, and iii) receive and demodulate the first waveform with the second demodulation pathway. The remodulation unit is configured to selectively i) output a first complex waveform based on the modulated signal, and ii) output a subsymbol waveform of the first waveform.

Abstract: A feedback equalizer includes a summing unit having an output and first input for receiving a modulated signal, which includes a symbol defined by a first number of chips. A subsymbol processor is coupled to the output of the summing unit. The symbol processor is capable of generating a subsymbol waveform upon receipt of a second number of chips of the symbol. The second number is less than the first number. A feedback filter is coupled to a second input of the summing unit and the symbol processing unit to selectively filter the subsymbol waveform from the modulated signal.

Abstract: A decoder comprises an equalizer that receives a modulated signal comprising a plurality of symbols including a first symbol defined by a first number of chips. A subsymbol processor that generates a subsymbol waveform after receiving a second number of chips of the first symbol and before at least one of receiving, decoding, and deciding the first number of chips of the first symbol. The second number is less than the first number, and wherein the equalizer equalizes the modulated signal using the subsymbol waveform.

Abstract: Techniques and instrumentalities to improve ISI and ICI cancellation in reception of modulated symbols by selectively decoding subsymbols of such modulated symbol before they can be completely decided or perceived as well as use of decoded symbol/subsymbol information in the feedback equalization process are disclosed. In particular, a decoder and corresponding method are disclosed which includes a feedback equalizer capable of receiving a modulated signal including a symbol defined by a first number of chips, along with a subsymbol processor to generate a subsymbol waveform upon receipt of a second number, less than the first number, of chips of such symbol and provide the subsymbol waveform to the feedback equalizer in order to equalize the modulated signal using the subsymbol waveform.