Abstract: A flash memory includes a linear array of flash memory cells having a source region extending along a first direction. Each flash memory cell includes a floating gate disposed adjacent the source region. The linear array of flash memory cells further includes isolation strips disposed between the floating gates of the flash memory cells. An erase gate line extends along the first direction and is disposed over the source region. A control gate line extends along the first direction and is disposed over the isolation strips and over the floating gates of the flash memory cells. The control gate line has a non-straight edge proximate to the source region that is indented away from the source region at least where the control gate line is disposed over the isolation strips.

Abstract: A heat dissipation system of an electronic device including a body, a plurality of heat sources disposed in the body, and at least one centrifugal heat dissipation fan disposed in the body is provided. The centrifugal heat dissipation fan includes a housing and an impeller disposed in the housing on an axis. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions, and the plurality of outlets respectively correspond to the plurality of heat sources.

Abstract: In some implementations, fluorine is oxidized after dry etching an oxide layer above a source/drain contact and before cleaning. Accordingly, less hydrofluoric acid is formed during cleaning, which reduces unexpected wet etching of the source/drain contact. This allows for forming a recess in the source/drain contact with a depth to width ratio in a range from approximately 1.0 to approximately 1.4 and prevents damage to a layer of silicide below the source/drain that can be caused by excessive hydrofluoric acid. Additionally, or alternatively, the recess is formed using multiple wet etch processes, and any residual fluorine is oxidized between the wet etch processes. Accordingly, each wet etching process may be shorter and less corrosive, which allows for greater control over dimensions of the recess. Additionally, less hydrofluoric acid may be formed during cleaning processes between the wet etch processes, which reduces the etching of the source/drain contact between processes.

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

Abstract: A system and method is provided for increasing a peak data rate achieved in HARQ feedback-disabled User Equipment (UE) in a Narrow Band Internet of Things (NB-IoT) non-terrestrial network (NTN) system where NB-IoT devices are connected to the gNodeB (gNB) through a satellite where a Downlink Control Information (DCI) N0 is received at the UE and the UE checks a Hybrid Automatic Repeat Request (HARQ) process number field to confirm the HARQ feedback is disabled, where the system determines an actual number of scheduled Transmission Blocks (TB) in an Uplink based on a New Data Indicator field and a Number of Scheduled TBs for Unicast field in the DCI N0. The actual number of scheduled TBs being greater than two without adding new bits to the DCI N0.

Abstract: The present disclosure provides an electronic device and a modulation method. The electronic device includes: a receiving unit, which is configured to obtain a first input bit sequence; and a control unit, which is configured to perform pseudo N-order first type modulation on the first input bit sequence, wherein N first symbols that may be obtained by means of the pseudo N-order first type modulation are a portion of second symbols that may be obtained by means of M-order second type modulation, M and N are positive integers, and M is greater than N.

Abstract: A method of forming a semiconductor device includes: forming an opening in a dielectric layer to expose an underlying conductive feature; conformally forming a first protection layer and a second protection layer in the opening; performing an anisotropic etching to remove a first portion of the second protection layer from the bottom of the opening while keeping a second portion of the second protection layer along the sidewalls of the opening; after the anisotropic etching, performing an isotropic etching to remove, from the sidewalls of the opening, an upper portion and a lower portion of the first protection layer while keeping a middle portion of the first protection layer along the sidewalls of the opening; after the isotropic etching, performing an anneal to at least partially convert the second portion of the second protection layer into an oxide; and after the anneal, filling the opening with a conductive material.

Abstract: Disclosed herein are NorA peptide inhibitors, protein scaffolds including the NorA peptide inhibitor, and antibody-based molecules that bind NorA, as well as compositions containing the same. Also disclosed are combinations therapeutic agents that include an antibiotic and/or biocide; and a NorA inhibitor, protein scaffold, or antibody-based as disclosed herein. Use of these agents for treating a Staphylococcus aureus infection, potentiating the therapeutic efficacy of an antibiotic or biocide, diagnosing a S. aureus infection, and detecting NorA in a non-clinical biological sample are also disclosed.

Abstract: A photovoltaic curtain wall and a method for manufacturing the photovoltaic curtain wall are provided. The photovoltaic curtain wall includes a first cover plate, a cell string, and a second cover plate stacked sequentially in a first direction; and an encapsulation film including a first adhesive film and a second adhesive film, the first adhesive film is attached to the first cover plate, and the second adhesive film is attached to the second cover plate. The second cover plate has a thickness greater than or equal to an equivalent thickness, and the first cover plate has a thickness less than the thickness of the second cover plate; and the equivalent thickness is a thickness of a target cover plate that undergoes a preset bending deformation in response to a preset load, and the target cover plate and the second cover plate is made of a same material.

Abstract: A photovoltaic curtain wall and a method for manufacturing the photovoltaic curtain wall are provided. The photovoltaic curtain wall includes a first cover plate, a cell string, and a second cover plate stacked sequentially in a first direction; and an encapsulation film including a first adhesive film and a second adhesive film, the first adhesive film is attached to the first cover plate, and the second adhesive film is attached to the second cover plate. The second cover plate has a thickness greater than or equal to an equivalent thickness, and the first cover plate has a thickness less than the thickness of the second cover plate; and the equivalent thickness is a thickness of a target cover plate that undergoes a preset bending deformation in response to a preset load, and the target cover plate and the second cover plate is made of a same material.

Abstract: A metal circuit structure based on a flexible printed circuit (FPC) contains: a substrate, a first metal layer attached on the substrate, a second metal layer formed on the first metal layer, and an intermediate layer defined between the first metal layer and the second metal layer. A first surface of the intermediate layer is connected with the first metal layer, and a second surface of the intermediate layer is connected with the second metal layer. The intermediate layer is made of a first material, the second metal layer is made of a second material, and the first material of the intermediate layer does not act with the second material of the second metal layer.

Abstract: A semiconductor device includes a semiconductor fin. The semiconductor device includes a metal gate disposed over the semiconductor fin. The semiconductor device includes a gate dielectric layer disposed between the semiconductor fin and the metal gate. The semiconductor device includes first spacers sandwiching the metal gate. The first spacers have a first top surface and the gate dielectric layer has a second top surface, and the first top surface and a first portion of the second top surface are coplanar with each other. The semiconductor device includes second spacers further sandwiching the first spacers. The second spacers have a third top surface above the first top surface and the second top surface. The semiconductor device includes a gate electrode disposed over the metal gate.

Abstract: A consensus method for a blockchain includes: obtaining, in a consensus reaching process of a block initiated by a proposal node, prevote messages generated by consensus nodes in a blockchain network; counting a quantity of first prevote messages for the block based on the received prevote messages, the first prevote messages being generated by the consensus nodes within a set duration in response to a proposal message for the block, the set duration corresponding to the proposal node and being determined based on a block generation duration of the proposal node; and adjusting the set duration corresponding to the proposal node recorded by the consensus nodes based on the quantity of the first prevote messages.

Abstract: An antenna package is provided. The antenna package includes a glass substrate, a plurality of antennas, a multi-layer circuit structure, and a plurality of radio frequency chips. The glass substrate has a first surface and a second surface. The plurality of antennas are arranged on the first surface of the glass substrate. The multi-layer circuit structure has a first surface and a second surface. The plurality of radio frequency chips are arranged on the first surface of the multi-layer circuit structure. The second surface of the glass substrate is adhered to the second surface of the multi-layer circuit structure.

Abstract: In some implementations, fluorine is oxidized after dry etching an oxide layer above a source/drain contact and before cleaning. Accordingly, less hydrofluoric acid is formed during cleaning, which reduces unexpected wet etching of the source/drain contact. This allows for forming a recess in the source/drain contact with a depth to width ratio in a range from approximately 1.0 to approximately 1.4 and prevents damage to a layer of silicide below the source/drain that can be caused by excessive hydrofluoric acid. Additionally, or alternatively, the recess is formed using multiple wet etch processes, and any residual fluorine is oxidized between the wet etch processes. Accordingly, each wet etching process may be shorter and less corrosive, which allows for greater control over dimensions of the recess. Additionally, less hydrofluoric acid may be formed during cleaning processes between the wet etch processes, which reduces the etching of the source/drain contact between processes.

Abstract: A flash memory includes a linear array of flash memory cells having a source region extending along a first direction. Each flash memory cell includes a floating gate disposed adjacent the source region. The linear array of flash memory cells further includes isolation strips disposed between the floating gates of the flash memory cells. An erase gate line extends along the first direction and is disposed over the source region. A control gate line extends along the first direction and is disposed over the isolation strips and over the floating gates of the flash memory cells. The control gate line has a non-straight edge proximate to the source region that is indented away from the source region at least where the control gate line is disposed over the isolation strips.

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

Abstract: An electronic package structure includes first and second package modules combined with each other. The first package module includes a substrate and a first electronic component disposed thereon, at least one second electronic component, and an insulation film. The first electronic component and the second electronic component are adjacent to each other. The insulation film includes a base material and a foam glue body, and the foam glue body is viscous and compressible. The second package module includes a heat dissipation plate and a liquid metal and an insulation protrusion portion disposed thereon. The liquid metal is pressed by the heat dissipation plate and the first electronic component. The insulation protrusion portion covers and abuts against the insulation film to press the foam glue body through the base material so as to deform the foam glue body and enable the foam glue body to cover the second electronic component.

Abstract: A method of monitoring viability of stem cell-derived cells used in stem cell therapy comprises introducing one or more stem cell-derived cells to a cell culture media, introducing one or more nanoprobes to the cell culture media, whereby the one or more stem cell-derived cells are transfected with the one or more nanoprobes, and detecting an optical signal from the one or more nanoprobes after transfection. The method may further comprise introducing the one or more transfected stem cell-derived cells to a subject and detecting the optical signal from the one or more nanoprobes in vivo. The one or more stem cell-derived cells may include a stem cell.