Abstract: In some implementations, one or more semiconductor processing tools may form a triple-stacked polysilicon structure on a substrate of a semiconductor device. The one or more semiconductor processing tools may form one or more polysilicon-based devices on the substrate of the semiconductor device, wherein the triple-stacked polysilicon structure has a first height that is greater than one or more second heights of the one or more polysilicon-based devices. The one or more semiconductor processing tools may perform a chemical-mechanical polishing (CMP) operation on the semiconductor device, wherein performing the CMP operation comprises using the triple-stacked polysilicon structure as a stop layer for the CMP operation.

Abstract: A method of forming a semiconductor device includes: forming a semiconductor structure having source/drain regions, a fin disposed between the source/drain regions, and a dummy gate disposed on the fin and surrounded by a spacer; removing the dummy gate to form a gate trench which is defined by a trench-defining wall; forming a gate dielectric layer on the trench-defining wall; forming a work function structure on the gate dielectric layer; forming a resist layer to fill the gate trench; removing a top portion of the resist layer; removing the work function structure exposed from the resist layer using a wet chemical etchant; removing the resist layer; and forming a conductive gate in the gate trench.

Abstract: The present disclosure provides a transmitting device and a receiving device. The transmitting device includes: a receiving unit configured to obtain a bit sequence to be transmitted; a control unit configured to determine a modulation and coding strategy (MCS) index according to information about phase noise; and a transmitting unit configured to transmit information about the MCS index.

Abstract: The present disclosure provides a transmitting device, a receiving device and a receiving method. The receiving device includes: a receiving unit configured to receive information about a modulation parameter indicating a spiral factor; a control unit configured to determine pseudo-N-order first type of modulation according to the modulation parameter, wherein 2{circumflex over (?)}N first symbols of the pseudo-N-order first type of modulation correspond to a part of 2{circumflex over (?)}M second symbols of M-order second type of modulation, and M and N are positive integers.

Abstract: Plasmonics-active nanoprobes are provided for detection of target biomolecules including nucleic acids, proteins, and small molecules. The nucleic acids that can be detected include RNA, DNA, mRNA, microRNA, and small nucleotide polymorphisms (SNPs). The nanoproprobes can be used in vito in sensitive detection methods for diagnosis of diseases and disorders including cancer. Multiplexing can be performed using the nanoprobes such that multiple targets can be detected simultaneously in a single sample. The methods of use of the nanoprobes include detection by a visible color change. The nanoprobes can be used in vivo for treatment of undesireable cells in a subject.

Abstract: To overcome the limitations of existing methods for detecting short nucleic acid molecules of low abundance such as miRNA, the present inventors provide a non-enzymatic signal amplification method based on inverse molecular sentinel (iMS) nanoprobes to improve detection sensitivity. The method is based on a cascade toehold-mediated DNA strand displacement reaction triggered by a “linear” DNA strand called “Recycling Trigger Probe” (RTP) strand. In the method, iMS-OFF nanoprobes are incubated with targets and RTP strands. After turning on the first nanoprobe, the target undergoes a recycling process triggered by the RTP strands. This process allows the target to turn on more iMS nanoprobes and provide an amplified SERS signal.

Abstract: A system and a method are provided for optimizing application of timing advance command (TAC) mechanism in a Narrow Band Internet of Things (NB-IoT) non-terrestrial network (NTN) system utilizes a timing advance (TA) estimation restriction duration. After one operation of a timing advance (TA) estimation resulting in issuing of an initial TAC, the gNB ignores the results of new TA estimations until specified X seconds after the initial TAC is sent. TA estimation restriction duration refers to the time duration between the initial TA estimation and X seconds after the initial TAC. The value of X is specified such that X represents the minimum duration starting from the transmission of the first TAC in which any received NPUSCH within this duration is not based on a new TAC. By applying the TA estimation restriction duration, multiple corrections of the same TA error are prevented.

Abstract: A flash memory includes a linear array of flash memory cells having a source region extending along a first direction. Each flash memory cell includes a floating gate disposed adjacent the source region. The linear array of flash memory cells further includes isolation strips disposed between the floating gates of the flash memory cells. An erase gate line extends along the first direction and is disposed over the source region. A control gate line extends along the first direction and is disposed over the isolation strips and over the floating gates of the flash memory cells. The control gate line has a non-straight edge proximate to the source region that is indented away from the source region at least where the control gate line is disposed over the isolation strips.

Abstract: A system and method is provided for increasing a peak data rate achieved in HARQ feedback-disabled User Equipment (UE) in a Narrow Band Internet of Things (NB-IoT) non-terrestrial network (NTN) system where NB-IoT devices are connected to the gNodeB (gNB) through a satellite where a Downlink Control Information (DCI) N0 is received at the UE and the UE checks a Hybrid Automatic Repeat Request (HARQ) process number field to confirm the HARQ feedback is disabled, where the system determines an actual number of scheduled Transmission Blocks (TB) in an Uplink based on a New Data Indicator field and a Number of Scheduled TBs for Unicast field in the DCI N0. The actual number of scheduled TBs being greater than two without adding new bits to the DCI N0.

Abstract: Disclosed herein are NorA peptide inhibitors, protein scaffolds including the NorA peptide inhibitor, and antibody-based molecules that bind NorA, as well as compositions containing the same. Also disclosed are combinations therapeutic agents that include an antibiotic and/or biocide; and a NorA inhibitor, protein scaffold, or antibody-based as disclosed herein. Use of these agents for treating a Staphylococcus aureus infection, potentiating the therapeutic efficacy of an antibiotic or biocide, diagnosing a S. aureus infection, and detecting NorA in a non-clinical biological sample are also disclosed.

Abstract: A consensus method for a blockchain includes: obtaining, in a consensus reaching process of a block initiated by a proposal node, prevote messages generated by consensus nodes in a blockchain network; counting a quantity of first prevote messages for the block based on the received prevote messages, the first prevote messages being generated by the consensus nodes within a set duration in response to a proposal message for the block, the set duration corresponding to the proposal node and being determined based on a block generation duration of the proposal node; and adjusting the set duration corresponding to the proposal node recorded by the consensus nodes based on the quantity of the first prevote messages.

Abstract: A flash memory includes a linear array of flash memory cells having a source region extending along a first direction. Each flash memory cell includes a floating gate disposed adjacent the source region. The linear array of flash memory cells further includes isolation strips disposed between the floating gates of the flash memory cells. An erase gate line extends along the first direction and is disposed over the source region. A control gate line extends along the first direction and is disposed over the isolation strips and over the floating gates of the flash memory cells. The control gate line has a non-straight edge proximate to the source region that is indented away from the source region at least where the control gate line is disposed over the isolation strips.

Abstract: A method of monitoring viability of stem cell-derived cells used in stem cell therapy comprises introducing one or more stem cell-derived cells to a cell culture media, introducing one or more nanoprobes to the cell culture media, whereby the one or more stem cell-derived cells are transfected with the one or more nanoprobes, and detecting an optical signal from the one or more nanoprobes after transfection. The method may further comprise introducing the one or more transfected stem cell-derived cells to a subject and detecting the optical signal from the one or more nanoprobes in vivo. The one or more stem cell-derived cells may include a stem cell.

Abstract: A honeycomb body having a repeating channel structure formed of intersecting porous walls. The repeating channel structure comprises a first channel type defined by at least four first surfaces, at least two of the at least four first surfaces are parallel to one another; and a second channel type having at least four second surfaces, wherein four or more of the at least four second surfaces are non-parallel with one another. Repeating channel structure is repeated in the honeycomb body. Honeycomb extrusion dies and methods of manufacturing the honeycomb body are provided, as are other embodiments.

Abstract: A flash memory includes a linear array of flash memory cells having a source region extending along a first direction. Each flash memory cell includes a floating gate disposed adjacent the source region. The linear array of flash memory cells further includes isolation strips disposed between the floating gates of the flash memory cells. An erase gate line extends along the first direction and is disposed over the source region. A control gate line extends along the first direction and is disposed over the isolation strips and over the floating gates of the flash memory cells. The control gate line has a non-straight edge proximate to the source region that is indented away from the source region at least where the control gate line is disposed over the isolation strips.

Abstract: Described are implementations for HARQ-disabling in IoT-NTN deployment AND disabling HARQ-ACK feedback. Signaling mechanisms include configurations for HARQ process ID(s), NPDCCH monitoring, a New Data Indicator (NDI) bit in Downlink Control Information (DCI), and a HARQ-ACK feedback transmission in the uplink.

Abstract: Articles and methods related to the cold-forming of glass laminate articles utilizing stress prediction analysis are provided. A cold-forming estimator (CFE) value that is related to the stress experienced by a glass sheet of a glass laminate during cold-forming is calculated based on a plurality of geometric parameters of glass layer(s) of a glass laminate article. The calculated CFE value is compared to a cold-forming threshold related to the probability that defects are formed in the complexly curved glass laminate article during cold-forming. Cold-formed glass laminate articles are also provided having geometric parameters such that the CFE value is below the cold-forming threshold.

Abstract: A flash memory includes a linear array of flash memory cells having a source region extending along a first direction. Each flash memory cell includes a floating gate disposed adjacent the source region. The linear array of flash memory cells further includes isolation strips disposed between the floating gates of the flash memory cells. An erase gate line extends along the first direction and is disposed over the source region. A control gate line extends along the first direction and is disposed over the isolation strips and over the floating gates of the flash memory cells. The control gate line has a non-straight edge proximate to the source region that is indented away from the source region at least where the control gate line is disposed over the isolation strips.

Abstract: Articles and methods related to the cold-forming of glass laminate articles utilizing stress prediction analysis are provided. A cold-forming estimator (CFE) value that is related to the stress experienced by a glass sheet of a glass laminate during cold-forming is calculated based on a plurality of geometric parameters of glass layer(s) of a glass laminate article. The calculated CFE value is compared to a cold-forming threshold related to the probability that defects are formed in the complexly curved glass laminate article during cold-forming. Cold-formed glass laminate articles are also provided having geometric parameters such that the CFE value is below the cold-forming threshold.

Abstract: The disclosure relates to performing phase compensation at a transmitter. A processing device for a network access node generates a phase compensated modulation symbol based on at least one first modulation symbol and at least on one of a frequency offset parameter and a time offset parameter. The frequency offset parameter may be determined based on an offset between a reference frequency f0 and a DC (0 Hz) frequency such that the frequency offset parameter corresponds to the reference frequency f0. Also, the reference frequency f0 can be at least partly based on the carrier of up-conversion frequency used by the processing device and the reference frequency f0 can be the carrier for up-conversion frequency. The phase compensated symbol is transmitted to a receiver, such as a client device. Furthermore, the disclosure also relates to corresponding methods and a computer program.