Patents by Inventor Neng Wang

Neng Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11975285
    Abstract: A honeycomb body having a repeating channel structure formed of intersecting porous walls. The repeating channel structure comprises a first channel type defined by at least four first surfaces, at least two of the at least four first surfaces are parallel to one another; and a second channel type having at least four second surfaces, wherein four or more of the at least four second surfaces are non-parallel with one another. Repeating channel structure is repeated in the honeycomb body. Honeycomb extrusion dies and methods of manufacturing the honeycomb body are provided, as are other embodiments.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: May 7, 2024
    Assignee: Corning Incorporated
    Inventors: Natarajan Gunasekaran, David Robert Heine, Weidong Li, Craig Louis Stratton, Neng Wang
  • Publication number: 20240145421
    Abstract: Provided are a passivation layer for forming a semiconductor bonding structure, a sputtering target making the same, a semiconductor bonding structure and a semiconductor bonding process. The passivation layer is formed on a bonding substrate by sputtering the sputtering target; the passivation layer and the sputtering target comprise a first metal, a second metal or a combination thereof. The bonding substrate comprises a third metal. Based on a total atom number of the surface of the passivation layer, O content of the surface of the passivation layer is less than 30 at %; the third metal content of the surface of the passivation layer is less than or equal to 10 at %. The passivation layer has a polycrystalline structure. The semiconductor bonding structure sequentially comprises a first bonding substrate, a bonding layer and a second bonding substrate: the bonding layer is mainly formed by the passivation layer and the third metal.
    Type: Application
    Filed: October 27, 2023
    Publication date: May 2, 2024
    Inventors: Kuan-Neng CHEN, Zhong-Jie HONG, Chih-I CHO, Ming-Wei WENG, Chih-Han CHEN, Chiao-Yen WANG, Ying-Chan HUNG, Hong-Yi WU, CHENG-YEN HSIEH
  • Publication number: 20240141922
    Abstract: A heat dissipation system of an electronic device including a body, a plurality of heat sources disposed in the body, and at least one centrifugal heat dissipation fan disposed in the body is provided. The centrifugal heat dissipation fan includes a housing and an impeller disposed in the housing on an axis. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions, and the plurality of outlets respectively correspond to the plurality of heat sources.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Applicant: Acer Incorporated
    Inventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Yu-Ming Lin, Wei-Chin Chen, Chun-Chieh Wang, Shu-Hao Kuo
  • Publication number: 20240136183
    Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Yu-Shih Wang, Hong-Jie Yang, Chia-Ying Lee, Po-Nan Yeh, U-Ting Chiu, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
  • Fan
    Patent number: 11946483
    Abstract: A fan is provided herein, including a housing, a hub, and a plurality of blades. The housing includes a top case and a bottom case. The hub is rotatably disposed between the top case and the bottom case in an axial direction. The blades extend from the hub in a radial direction, located between the top case and the bottom case. Each of the blades has a proximal end and a distal end. The proximal end is connected to the hub. The distal end is opposite from the proximal end, located at the other side of the blade, having at least one recessed portion. Each of the recessed portions form a passage for air.
    Type: Grant
    Filed: May 17, 2023
    Date of Patent: April 2, 2024
    Assignee: ACER INCORPORATED
    Inventors: Jau-Han Ke, Tsung-Ting Chen, Chun-Chieh Wang, Yu-Ming Lin, Cheng-Wen Hsieh, Wen-Neng Liao
  • Publication number: 20240068754
    Abstract: A heat dissipation module used for an electronic device is provided. The electronic device has a heat source. The heat dissipation module includes an evaporator, a plurality of heat conducting components, a pipe connected to the evaporator to form a loop, and a working fluid filled in the loop. An exterior of the evaporator has a heat conducting zone thermally contacted with the heat source to absorb heat generated from the heat source. The heat conducting components are disposed in the evaporator, located at an interior of the evaporator corresponding to the heat conducting zone. The heat conducting components are in pillar shape or rib shape respectively. The working fluid in liquid passes through the evaporator, absorbs heat, and is transformed into vapor to flow out of the evaporator. Each of the heat conducting components in rib shape is oriented in a flow direction of the working fluid.
    Type: Application
    Filed: November 9, 2023
    Publication date: February 29, 2024
    Applicant: Acer Incorporated
    Inventors: Yung-Chih Wang, Jau-Han Ke, Wen-Neng Liao, Cheng-Wen Hsieh
  • Patent number: 11914432
    Abstract: A portable electronic device including a first body, a second body, a pivot element, a heat source, a first flexible heat conductive element, and a flip cover is provided. The pivot element is connected to the second body, and the second body is pivotally connected to the first body through the pivot element. The heat source is disposed in the first body. The first flexible heat conductive element is thermally coupled to the heat source and extends toward the pivot element from the heat source. The first flexible heat conductive element passes through the pivot element and extends into the inside of the second body and is thus thermally coupled to the second body. The flip cover is pivotally connected to the first body and located on a moving path of the pivot element.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: February 27, 2024
    Assignee: Acer Incorporated
    Inventors: Chun-Chieh Wang, Wen-Neng Liao, Cheng-Wen Hsieh, Chuan-Hua Wang, Yi-Ta Huang
  • Patent number: 11913472
    Abstract: A centrifugal heat dissipation fan including a housing and an impeller disposed in the housing on an axis is provided. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions. A heat dissipation system of an electronic device is also provided.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: February 27, 2024
    Assignee: Acer Incorporated
    Inventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Yu-Ming Lin, Wei-Chin Chen, Chun-Chieh Wang, Shu-Hao Kuo
  • Publication number: 20230371250
    Abstract: A flash memory includes a linear array of flash memory cells having a source region extending along a first direction. Each flash memory cell includes a floating gate disposed adjacent the source region. The linear array of flash memory cells further includes isolation strips disposed between the floating gates of the flash memory cells. An erase gate line extends along the first direction and is disposed over the source region. A control gate line extends along the first direction and is disposed over the isolation strips and over the floating gates of the flash memory cells. The control gate line has a non-straight edge proximate to the source region that is indented away from the source region at least where the control gate line is disposed over the isolation strips.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Inventors: Shun-Neng Wang, Tung-Huang Chen, Ching-Hung Kao
  • Publication number: 20230361972
    Abstract: Described are implementations for HARQ-disabling in IoT-NTN deployment AND disabling HARQ-ACK feedback. Signaling mechanisms include configurations for HARQ process ID(s), NPDCCH monitoring, a New Data Indicator (NDI) bit in Downlink Control Information (DCI), and a HARQ-ACK feedback transmission in the uplink.
    Type: Application
    Filed: April 27, 2023
    Publication date: November 9, 2023
    Applicant: Mavenir Systems, Inc.
    Inventors: Neng WANG, Young-Han NAM, Sina KHOSHABI-NOBAR
  • Patent number: 11795095
    Abstract: Articles and methods related to the cold-forming of glass laminate articles utilizing stress prediction analysis are provided. A cold-forming estimator (CFE) value that is related to the stress experienced by a glass sheet of a glass laminate during cold-forming is calculated based on a plurality of geometric parameters of glass layer(s) of a glass laminate article. The calculated CFE value is compared to a cold-forming threshold related to the probability that defects are formed in the complexly curved glass laminate article during cold-forming. Cold-formed glass laminate articles are also provided having geometric parameters such that the CFE value is below the cold-forming threshold.
    Type: Grant
    Filed: February 24, 2023
    Date of Patent: October 24, 2023
    Assignee: Corning Incorporated
    Inventors: Vikram Bhatia, Ah-Young Park, Yousef Kayed Qaroush, Neng Wang
  • Publication number: 20230328972
    Abstract: A flash memory includes a linear array of flash memory cells having a source region extending along a first direction. Each flash memory cell includes a floating gate disposed adjacent the source region. The linear array of flash memory cells further includes isolation strips disposed between the floating gates of the flash memory cells. An erase gate line extends along the first direction and is disposed over the source region. A control gate line extends along the first direction and is disposed over the isolation strips and over the floating gates of the flash memory cells. The control gate line has a non-straight edge proximate to the source region that is indented away from the source region at least where the control gate line is disposed over the isolation strips.
    Type: Application
    Filed: April 6, 2022
    Publication date: October 12, 2023
    Inventors: Shun-Neng Wang, Tung-Huang Chen, Ching-Hung Kao
  • Publication number: 20230242434
    Abstract: Articles and methods related to the cold-forming of glass laminate articles utilizing stress prediction analysis are provided. A cold-forming estimator (CFE) value that is related to the stress experienced by a glass sheet of a glass laminate during cold-forming is calculated based on a plurality of geometric parameters of glass layer(s) of a glass laminate article. The calculated CFE value is compared to a cold-forming threshold related to the probability that defects are formed in the complexly curved glass laminate article during cold-forming. Cold-formed glass laminate articles are also provided having geometric parameters such that the CFE value is below the cold-forming threshold.
    Type: Application
    Filed: February 24, 2023
    Publication date: August 3, 2023
    Inventors: Vikram Bhatia, Ah-Young Park, Yousef Kayed Qaroush, Neng Wang
  • Patent number: 11695606
    Abstract: The disclosure relates to performing phase compensation at a transmitter. A processing device for a network access node generates a phase compensated modulation symbol based on at least one first modulation symbol and at least on one of a frequency offset parameter and a time offset parameter. The frequency offset parameter may be determined based on an offset between a reference frequency f0 and a DC (0 Hz) frequency such that the frequency offset parameter corresponds to the reference frequency f0. Also, the reference frequency f0 can be at least partly based on the carrier of up-conversion frequency used by the processing device and the reference frequency f0 can be the carrier for up-conversion frequency. The phase compensated symbol is transmitted to a receiver, such as a client device. Furthermore, the disclosure also relates to corresponding methods and a computer program.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: July 4, 2023
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Wenquan Hu, Bengt Lindoff, Jingxin Wei, Neng Wang, Qian Zhang
  • Publication number: 20230169656
    Abstract: A diagnostic mobile health system for detecting biomarkers comprises an electronic device including an image sensor configured to capture image data, a sample housing configured to removably attach to the electronic device, and a computing device including at least one processor. The sample housing includes a slot to receive a sample container. The sample container received in the slot is positioned to allow the image sensor to capture image data for the sample when the sample housing is attached to the electronic device. The processor is configured for receiving, from the electronic device, image data for the sample that is captured by the image sensor of the electronic device when the sample container containing the sample is received by the sample housing attached to the electronic device and detecting at least one biomarker for the sample based on the received image data.
    Type: Application
    Filed: November 30, 2022
    Publication date: June 1, 2023
    Inventors: Tuan VO-DINH, Tushar KRISHNAN, Hsin-Neng WANG
  • Publication number: 20230155036
    Abstract: In some implementations, one or more semiconductor processing tools may form a triple-stacked polysilicon structure on a substrate of a semiconductor device. The one or more semiconductor processing tools may form one or more polysilicon-based devices on the substrate of the semiconductor device, wherein the triple-stacked polysilicon structure has a first height that is greater than one or more second heights of the one or more polysilicon-based devices. The one or more semiconductor processing tools may perform a chemical-mechanical polishing (CMP) operation on the semiconductor device, wherein performing the CMP operation comprises using the triple-stacked polysilicon structure as a stop layer for the CMP operation.
    Type: Application
    Filed: January 23, 2023
    Publication date: May 18, 2023
    Inventors: Chi-Chung JEN, Ya-Chi HUNG, Yu-Chun SHEN, Shun-Neng WANG, Wen-Chih CHIANG
  • Patent number: 11632208
    Abstract: Channel covariance feedback is disclosed for enhanced full-dimension multiple input, multiple output (eFD-MIMO) systems. Channel state information (CSI) reference signal (CSI-RS) feedback operations are implemented using spatial covariance feedback of a covariance estimate. After obtaining a set of orthogonal basis vectors, a user equipment (UE) measures the CSI-RS from a base station and determines the spatial covariance matrix from the signal. The UE may then compress the spatial covariance matrix into a lower-dimension covariance estimate matrix using the orthogonal basis vectors. The lower-dimension matrix along with element-wise quantization allows for feedback of spatial covariance for eFD-MIMO systems without excessive feedback overhead.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: April 18, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Bo Chen, Chao Wei, Liangming Wu, Neng Wang
  • Patent number: 11591249
    Abstract: Articles and methods related to the cold-forming of glass laminate articles utilizing stress prediction analysis are provided. A cold-forming estimator (CFE) value that is related to the stress experienced by a glass sheet of a glass laminate during cold-forming is calculated based on a plurality of geometric parameters of glass layer(s) of a glass laminate article. The calculated CFE value is compared to a cold-forming threshold related to the probability that defects are formed in the complexly curved glass laminate article during cold-forming. Cold-formed glass laminate articles are also provided having geometric parameters such that the CFE value is below the cold-forming threshold.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: February 28, 2023
    Assignee: Corning Incorporated
    Inventors: Vikram Bhatia, Ah-Young Park, Yousef Kayed Qaroush, Neng Wang
  • Patent number: 11578296
    Abstract: A closure assembly is provided. The closure assembly includes a cap portion, a tubular neck extending from a top surface of the cap portion, and at least one reinforcing member extending between the top surface of the cap portion and an exterior surface of the tubular neck, wherein the cap portion, the tubular neck and the at least one reinforcing member are a unitary integral piece. The closure assembly design provides stability to the tubular neck and the cap portion when a force is applied to either one or both of the tubular neck and the cap portion.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: February 14, 2023
    Assignee: CORNING INCORPORATED
    Inventors: James M. Philippe, Aravind Raghavan Rammohan, Paul Kevin Seeto, Neng Wang
  • Patent number: 11563127
    Abstract: In some implementations, one or more semiconductor processing tools may form a triple-stacked polysilicon structure on a substrate of a semiconductor device. The one or more semiconductor processing tools may form one or more polysilicon-based devices on the substrate of the semiconductor device, wherein the triple-stacked polysilicon structure has a first height that is greater than one or more second heights of the one or more polysilicon-based devices. The one or more semiconductor processing tools may perform a chemical-mechanical polishing (CMP) operation on the semiconductor device, wherein performing the CMP operation comprises using the triple-stacked polysilicon structure as a stop layer for the CMP operation.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: January 24, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Chung Jen, Ya-Chi Hung, Yu-Chun Shen, Shun-Neng Wang, Wen-Chih Chiang