Patents by Inventor Neng-Wei Wu

Neng-Wei Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130044201
    Abstract: A hand-held fluorescence microscope is disclosed, including: a partial-spectrum light source, a first filtering device, a second filtering device, and an image sensor arranged inside a housing of the hand-held fluorescence microscope. The partial-spectrum light source generates a first light beam. The first filtering device filters the first light beam to provide a second light beam. The second filtering device filters a fluorescence generated by a specimen after receiving the second light beam to provide a fourth light beam. The image sensor receives the fourth light beam to generate fluorescence images. One end of the housing is provided with a light mask for surrounding the specimen to avoid external light from being entering the image sensor. The light path of the second light beam projecting to the specimen does not overlap with the light path of the fluorescence radiating from the specimen to the second filtering device.
    Type: Application
    Filed: August 8, 2012
    Publication date: February 21, 2013
    Applicant: AnMo Electronics Corporation
    Inventor: Paul Neng-Wei WU
  • Patent number: 8358851
    Abstract: A computer program product capable of enabling a computer to perform a digital image analyzing operation, wherein the digital image analyzing operation comprises: receiving settings of a plurality of lines corresponding to one or more image edges of a digital image; and identifying a plurality of intersections of the plurality of lines and the one or more image edges of the digital image.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: January 22, 2013
    Assignee: Anmo Electronics Corporation
    Inventor: Paul Neng-Wei Wu
  • Publication number: 20120062721
    Abstract: A digital microscope is disclosed including: an image sensing circuit having an image sensing area thereon; a first object lens aligned with the image sensing area along an axis; a luminance device positioned outside the axis for emitting light toward a direction that is not coaxial with the axis; a light redirector positioned outside the axis for redirecting the light emitted from the luminance device; and a beam splitter positioned on the axis for changing the direction of light from the light redirector to provide an output light that is outputted substantially along the axis and coaxial with the axis; wherein the first object lens is positioned between the image sensing area and the beam splitter.
    Type: Application
    Filed: November 23, 2010
    Publication date: March 15, 2012
    Inventor: Paul Neng-Wei WU
  • Publication number: 20110261209
    Abstract: A digital imaging apparatus is disclosed including: a light source module; an image synchronization signal generator for generating an image synchronization signal; and a light source controller, coupled with the light source module and the image synchronization signal generator, for generating a light source control signal having a frequency corresponding to the image synchronization signal and synchronized with the image synchronization signal to control the light output of the light source module.
    Type: Application
    Filed: September 16, 2010
    Publication date: October 27, 2011
    Applicant: AnMo Electronics Corporation
    Inventor: Paul Neng-Wei WU
  • Publication number: 20110235917
    Abstract: A computer program product capable of enabling a computer to perform a digital image analyzing operation, wherein the digital image analyzing operation comprises: receiving settings of a plurality of lines corresponding to one or more image edges of a digital image; and identifying a plurality of intersections of the plurality of lines and the one or more image edges of the digital image.
    Type: Application
    Filed: July 21, 2010
    Publication date: September 29, 2011
    Inventor: Paul Neng-Wei WU
  • Publication number: 20100171827
    Abstract: An optical inspection apparatus is disclosed including: a digital image sensing module, a light source, a detachable light guide configured for guiding incident light to transmit within the detachable light guide and to output from a first angle, and an adapter engaged with the digital image sensing module for guiding light emitted from the light source to the detachable light guide; wherein the detachable light guide is detachably engaged with the adapter.
    Type: Application
    Filed: January 7, 2009
    Publication date: July 8, 2010
    Inventor: Paul Neng-Wei Wu
  • Publication number: 20100112511
    Abstract: A reflecting-type optical inspection apparatus is disclosed including: a holding portion configured for detachably holding an external device having a reflective surface; a connecting portion engaged with the holding portion; and a digital image sensing module engaged with the connecting portion for sensing light reflected from the reflective surface of the external device.
    Type: Application
    Filed: November 4, 2008
    Publication date: May 6, 2010
    Inventor: Paul Neng-Wei Wu
  • Publication number: 20080193894
    Abstract: A mouth camera device has a camera and a mouth mirror. The camera has a handle, a lens, a photo sensor assembly, a PCB assembly and a computer output port. The computer output port is connected to a computer. The mouth mirror is mounted detachably in the handle. The camera may catch and transmit static or dynamic images to the computer so a diagnostician and a patient may clearly and easily watch a condition inside the patient's mouth cavity. Diagnosing the mouth cavity is convenient and timesaving.
    Type: Application
    Filed: February 13, 2007
    Publication date: August 14, 2008
    Inventor: Neng-Wei Wu
  • Patent number: 5895250
    Abstract: A method for making semicrown stacked capacitors for DRAM devices is achieved. A first insulating layer, a second insulating etch-stop layer, and a high-etch-rate third insulating layer are sequentially formed on a substrate over the memory cell areas having FETs with source/drain areas. Recesses are etched in the third and second insulating layers for bottom electrodes, aligned over device areas. Node contact openings are plasma etched in the first insulating layer exposed in the recesses to one of each source/drain area. A first polysilicon layer is deposited to form node contacts and the bottom electrodes. A high-etch-rate fourth insulating layer is used to fill the recesses. The fourth insulating layer and the first polysilicon layer are etched or chem/mech polished back to form the array of bottom electrodes having oxide plugs. The plugs and third insulating layer are wet etched to the etch-stop layer to form the semicrown bottom electrodes.
    Type: Grant
    Filed: June 11, 1998
    Date of Patent: April 20, 1999
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Neng-Wei Wu
  • Patent number: 5317178
    Abstract: A field effect transistor having a thin polycrystalline silicon layer as a channel region, a lower gate electrode beneath the silicon layer, and upper gate electrode with an offset above the silicon layer, and a gate dielectric layer between the lower gate electrode and the silicon layer, and a gate dielectric layer between the upper gate electrode and the silicon layer.
    Type: Grant
    Filed: July 22, 1993
    Date of Patent: May 31, 1994
    Assignee: Industrial Technology Research Institute
    Inventor: Neng-Wei Wu
  • Patent number: 5266507
    Abstract: A method of fabricating an offset dual gate thin film field offset transistor wherein a lower gate electrode is formed on an insulating substrate is provided. A dielectric layer deposited. A polycrystalline silicon layer deposited and patterned to overlie and extend beyond the edges of the lower gate. A dielectric layer deposited. A metal layer deposited. A photoresist layer deposited and patterned to define a upper gate electrode in the metal layer that overlies the lower gate electrode but extend beyond one edge. The exposed metal layer is removed to form the upper gate electrode. An impurity is ion implanted into the polycrystalline silicon layer to form source and drain regions, using the photoresist layer and metal layer as a mask.
    Type: Grant
    Filed: May 18, 1992
    Date of Patent: November 30, 1993
    Assignee: Industrial Technology Research Institute
    Inventor: Neng-Wei Wu
  • Patent number: 5208472
    Abstract: A method of forming a self-aligned metal oxide semiconductor (MOS) structure is described. Multilayer dielectrics are used at the edge of the gate electrode, and the gate electrode, the source and the drain have metal silicide regions. The first layer of dielectric is used to define a lightly doped drain (LDD) structure and the second dielectric layer serves to extend the oxide region at the gate edge and to improve the source/drain junction leakage property and to reduce the shorting percentage of gate to source/drain. A special device structure with extended lateral diffusion of junction under the oxide at the gate edge will be performed by using this method.
    Type: Grant
    Filed: June 3, 1992
    Date of Patent: May 4, 1993
    Assignee: Industrial Technology Research Institute
    Inventors: Wen-Doe Su, Neng-Wei Wu
  • Patent number: 5151374
    Abstract: A process for forming a thin film field effect transistor, particularly adapted for use in SDRAM devices using CMOS flip-flop circuits, wherein the transistor has a drain-channel P-N junction that is precisely spaced from the gate electrode, the process involving the etch back of the edge of the gate electrode, either prior to ion implantation to form the source and drain, or following the implantation.
    Type: Grant
    Filed: July 24, 1991
    Date of Patent: September 29, 1992
    Assignee: Industrial Technology Research Institute
    Inventor: Neng-Wei Wu
  • Patent number: 4908332
    Abstract: A process for reducing gate sheet resistance in VSLI devices employs planarization and metal refilling to produce a gate of layers of polysilicon and pure metal. The polysilicon underlayer maintains the characteristics of a polysilicon gate and the metal layer reduces the gate sheet resistance. The process includes the etching back of the planarized dielectric (6) to expose the top surface of the polysilicon gate (3), the etching of the polysilicon to form a groove, and the filling of the groove with a metal, e.g. W, by selective or blanket CVD.
    Type: Grant
    Filed: May 4, 1989
    Date of Patent: March 13, 1990
    Assignee: Industrial Technology Research Institute
    Inventor: Neng-Wei Wu