Patents by Inventor Nerinder Singh

Nerinder Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9007079
    Abstract: An IDDQ test system and method that, in one embodiment, includes 1) an empirical extraction subsystem operable to generate an IDDQ versus temperature model for a given semiconductor device design, 2) an automatic test equipment (ATE) test subsystem operable to obtain a measured IDDQ value (IDDQm) at a measured temperature (Tm) for a specific semiconductor device embodying the given semiconductor device design, the measured temperature (Tm) obtained within 5 seconds of obtaining the measured IDDQ value (IDDQm), and 3) a scaling subsystem operable to scale the measured IDDQ value (IDDQm) at the measured temperature (Tm) to a compensated IDDQ value (IDDQc) at a desired temperature (Td) using the IDDQ versus temperature model.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: April 14, 2015
    Assignee: Nvidia Corporation
    Inventors: Dushyant Narayen, Nerinder Singh, Gunaseelan Ponnuvel, Hemant Kumar, Luai Nasser, Craig Nishizaki
  • Publication number: 20140214342
    Abstract: A system, method, and computer program product are provided for verifying sensitivity test program stability. A sensitivity test program including a set of tests is run on a plurality of integrated circuit die fabricated on a silicon wafer, where each test in the set of tests specifies a different set of operating parameters for structures within each integrated circuit die. Results of the sensitivity test program are received for each integrated circuit die and the results of the sensitivity test program are stored in shadow bins allocated within a memory, where each shadow bin corresponds to a different test in the set of tests. The results may be used to verify and optimize operating voltage and operating frequency of different tests in the production test program and wafer fabrication process sensitivity.
    Type: Application
    Filed: January 30, 2013
    Publication date: July 31, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Gunaseelan Ponnuvel, Keith Michael Katcher, Tsung-Chi Eddy Yang, Nerinder Singh
  • Publication number: 20140125364
    Abstract: An IDDQ test system and method that, in one embodiment,deg includes 1) an empirical extraction subsystem operable to generate an IDDQ versus temperature model for a given semiconductor device design, 2) an automatic test equipment (ATE) test subsystem operable to obtain a measured IDDQ value (IDDQm) at a measured temperature (Tm) for a specific semiconductor device embodying the given semiconductor device design, the measured temperature (Tm) obtained within 5 seconds of obtaining the measured IDDQ value (IDDQm), and 3) a scaling subsystem operable to scale the measured IDDQ value (IDDQm) at the measured temperature (Tm) to a compensated IDDQ value (IDDQc) at a desired temperature (Td) using the IDDQ versus temperature model.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 8, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Dushyant Narayen, Nerinder Singh, Gunaseelan Ponnuvel, Hemant Kumar, Luai Nasser, Craig Nishizaki