Patents by Inventor Nerissa Draeger

Nerissa Draeger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190393046
    Abstract: A method for selectively etching a dielectric layer with respect to an epitaxial layer or metal-based hardmask is provided. The method comprises performing a plurality of cycles. Each cycle comprises a deposition phase and an activation phase. The deposition phase comprises flowing a deposition gas, wherein the deposition gas comprises helium and a hydrofluorocarbon or fluorocarbon, forming the deposition gas into a plasma to effect a fluorinated polymer deposition, and stopping the flow of the deposition gas. The activation phase comprises flowing an activation gas comprising an ion bombardment gas, forming the activation gas into a plasma, providing an activation bias to cause ion bombardment of the fluorinated polymer deposition, wherein the ion bombardment activates fluorine from the fluorinated polymer deposition to etch the dielectric layer, and stopping the flow of the activation gas.
    Type: Application
    Filed: June 26, 2018
    Publication date: December 26, 2019
    Inventors: Chia-Chun WANG, Eric HUDSON, Andrew Clark SERINO, Nerissa DRAEGER, Zhonghao ZHANG
  • Patent number: 10354887
    Abstract: A method for etching a metal oxide layer on a semiconductor substrate, comprising providing a plurality of cycles, is provided. Each cycle comprises exposing the metal oxide layer to a reactive hydrogen-containing gas or plasma to transform a part of the metal oxide layer into a layer of metal hydride, stopping the exposing the metal oxide layer to the reactive hydrogen-containing gas or plasma, heating the layer of metal hydride to at least a sublimation temperature to sublime the layer of metal hydride, and cooling the metal oxide layer to a temperature below the sublimation temperature.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: July 16, 2019
    Assignee: Lam Research Corporation
    Inventors: Andreas Fischer, Nerissa Draeger
  • Publication number: 20190096690
    Abstract: A method for etching a metal oxide layer on a semiconductor substrate, comprising providing a plurality of cycles, is provided. Each cycle comprises exposing the metal oxide layer to a reactive hydrogen-containing gas or plasma to transform a part of the metal oxide layer into a layer of metal hydride, stopping the exposing the metal oxide layer to the reactive hydrogen-containing gas or plasma, heating the layer of metal hydride to at least a sublimation temperature to sublime the layer of metal hydride, and cooling the metal oxide layer to a temperature below the sublimation temperature.
    Type: Application
    Filed: September 27, 2017
    Publication date: March 28, 2019
    Inventors: Andreas FISCHER, Nerissa DRAEGER
  • Patent number: 9847222
    Abstract: Provided herein are methods and apparatus for improved flowable dielectric deposition on substrate surfaces. The methods involve improving nucleation and wetting on the substrate surface without forming a thick high wet etch rate interface layer. According to various embodiments, the methods may include single or multi-stage remote plasma treatments of a deposition surface. In some embodiments, a treatment may include exposure to both a reducing chemistry and a hydrogen-containing oxidizing chemistry. Apparatus for performing the methods are also provided.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: December 19, 2017
    Assignee: Lam Research Corporation
    Inventors: Patrick Reilly, Harald te Nijenhuis, Nerissa Draeger, Bart J. van Schravendijk, Nicholas Muga Ndiege
  • Patent number: 9627608
    Abstract: Systems and method include providing a non-volatile random access memory (NVRAM) stack including a plurality of layers. The plurality of layers includes a dielectric layer and a metal layer. The metal layer of the NVRAM stack is patterned. The patterning causes damage to lateral side portions of the dielectric layer. The lateral portions of the dielectric layer are repaired by depositing dielectric material on the lateral side portions of the dielectric layer.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: April 18, 2017
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Nerissa Draeger, Thorsten Lill, Diane Hymes
  • Patent number: 9299559
    Abstract: Provided herein are integration-compatible dielectric films and methods of depositing and modifying them. According to various embodiments, the methods can include deposition of flowable dielectric films targeting specific film properties and/or modification of those properties with an integration-compatible treatment process. In certain embodiments, methods of depositing and modifying flowable dielectric films having tunable wet etch rates and other properties are provided. Wet etch rates can be tuned during integration through am integration-compatible treatment process. Examples of treatment processes include plasma exposure and ultraviolet radiation exposure.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: March 29, 2016
    Assignee: Novellus Systems, Inc.
    Inventors: Nerissa Draeger, Karena Shannon, Bart van Schravendijk, Kaihan Ashtiani
  • Publication number: 20160079521
    Abstract: Systems and method include providing a non-volatile random access memory (NVRAM) stack including a plurality of layers. The plurality of layers includes a dielectric layer and a metal layer. The metal layer of the NVRAM stack is patterned. The patterning causes damage to lateral side portions of the dielectric layer. The lateral portions of the dielectric layer are repaired by depositing dielectric material on the lateral side portions of the dielectric layer.
    Type: Application
    Filed: September 11, 2014
    Publication date: March 17, 2016
    Inventors: Nerissa Draeger, Thorsten Lill, Diane Hymes
  • Publication number: 20160042945
    Abstract: A method includes depositing a film solution onto a patterned feature of a semiconductor substrate after wet cleaning the semiconductor substrate and without performing a drying step after the wet cleaning. The film solution includes a dielectric film precursor or a dielectric film precursor and at least one of a reactant, a solvent, a surfactant and a carrier fluid. The method includes baking at least one of solvent and unreacted solution out of a film formed by the film solution by heating the substrate to a baking temperature. The method includes curing the substrate.
    Type: Application
    Filed: August 11, 2014
    Publication date: February 11, 2016
    Inventors: Ratchana Limary, Nerissa Draeger, Diane Hymes, Richard Gottscho
  • Patent number: 9257302
    Abstract: Provided are methods of filling gaps on a substrate by creating flowable silicon oxide-containing films. The methods involve introducing vapor-phase silicon-containing precursor and oxidant reactants into a reaction chamber containing the substrate under conditions such that a condensed flowable film is formed on the substrate. The flowable film at least partially fills gaps on the substrate. In certain embodiments, the methods involve using a catalyst in the formation of the film. The catalyst may be incorporated into one of the reactants and/or introduced as a separate reactant.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: February 9, 2016
    Assignee: Novellus Systems, Inc.
    Inventors: Feng Wang, Brian Lu, Nerissa Draeger, Vishal Gauri, Raashina Humayun, Michal Danek, Bart van Schravendijk, Lakshminarayana Nittala
  • Patent number: 9064684
    Abstract: Methods and apparatus for filling gaps on partially manufactured semiconductor substrates with dielectric material are provided. In certain embodiments, the methods include introducing a first process gas into the processing chamber and accumulating a second process gas in an accumulator maintained at a pressure level substantially highest than that of the processing chamber pressure level. The second process gas is then rapidly introduced from the accumulator into the processing chamber. An excess amount of the second process gas may be provided in the processing chamber during the introduction of the second process gas. Flowable silicon-containing films forms on a surface of the substrate to at least partially fill the gaps.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: June 23, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Collin K. L. Mui, Lakshminarayana Nittala, Nerissa Draeger
  • Publication number: 20150118862
    Abstract: Provided herein are methods and apparatus for improved flowable dielectric deposition on substrate surfaces. The methods involve improving nucleation and wetting on the substrate surface without forming a thick high wet etch rate interface layer. According to various embodiments, the methods may include single or multi-stage remote plasma treatments of a deposition surface. In some embodiments, a treatment may include exposure to both a reducing chemistry and a hydrogen-containing oxidizing chemistry. Apparatus for performing the methods are also provided.
    Type: Application
    Filed: October 21, 2014
    Publication date: April 30, 2015
    Inventors: Patrick Reilly, Harald te Nijenhuis, Nerissa Draeger, Bart J. van Schravendijk, Nicholas Muga Ndiege
  • Publication number: 20150118848
    Abstract: Higher overall etch rate and throughput for atomic layer removal (ALR) is achieved. The reaction is a self-limiting process, thus limiting the total amount of material that may be etched per cycle. By pumping down the process station between reacting operations, the reaction is partially “reset.” A higher overall etch rate is achieved by a multiple exposure with pump down ALR process.
    Type: Application
    Filed: November 3, 2014
    Publication date: April 30, 2015
    Inventors: Nerissa Draeger, Harald te Nijenhuis, Henner Meinhold, Bart van Schravendijk, Lakshmi Nittala
  • Publication number: 20150118863
    Abstract: Provided herein are methods and apparatus for forming flowable dielectric films having low porosity. In some embodiments, the methods involve plasma post-treatments of flowable dielectric films. The treatments can involve exposing a flowable film to a plasma while the film is still in a flowable, reactive state but after deposition of new material has ceased.
    Type: Application
    Filed: October 21, 2014
    Publication date: April 30, 2015
    Inventors: Megha Rathod, Deenesh Padhi, Nerissa Draeger, Bart J. van Schravendijk, Kaihan Ashtiani
  • Publication number: 20150044882
    Abstract: Provided herein are integration-compatible dielectric films and methods of depositing and modifying them. According to various embodiments, the methods can include deposition of flowable dielectric films targeting specific film properties and/or modification of those properties with an integration-compatible treatment process. In certain embodiments, methods of depositing and modifying flowable dielectric films having tunable wet etch rates and other properties are provided. Wet etch rates can be tuned during integration through am integration-compatible treatment process. Examples of treatment processes include plasma exposure and ultraviolet radiation exposure.
    Type: Application
    Filed: August 22, 2014
    Publication date: February 12, 2015
    Inventors: Nerissa Draeger, Karena Shannon, Bart van Schravendijk, Kaihan Ashtiani
  • Publication number: 20140302689
    Abstract: Methods for depositing flowable dielectric films are provided. In some embodiments, the methods involve introducing a silicon-containing precursor to a deposition chamber wherein the precursor is characterized by having a partial pressure:vapor pressure ratio between 0.01 and 1. In some embodiments, the methods involve depositing a high density plasma dielectric film on a flowable dielectric film. The high density plasma dielectric film may fill a gap on a substrate. Also provided are apparatuses for performing the methods.
    Type: Application
    Filed: April 9, 2014
    Publication date: October 9, 2014
    Applicant: Novellus Systems, Inc.
    Inventors: Kaihan Ashtiani, Michael Wood, John Drewery, Naohiro Shoda, Bart van Schravendijk, Lakshminarayana Nittala, Nerissa Draeger
  • Patent number: 8846536
    Abstract: Provided herein are integration-compatible dielectric films and methods of depositing and modifying them. According to various embodiments, the methods can include deposition of flowable dielectric films targeting specific film properties and/or modification of those properties with an integration-compatible treatment process. In certain embodiments, methods of depositing and modifying flowable dielectric films having tunable wet etch rates and other properties are provided. Wet etch rates can be tuned during integration through am integration-compatible treatment process. Examples of treatment processes include plasma exposure and ultraviolet radiation exposure.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: September 30, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Nerissa Draeger, Karena Shannon, Bart van Schravendijk, Kaihan Ashtiani
  • Patent number: 8728958
    Abstract: Novel gap fill schemes involving depositing both flowable oxide films and high density plasma chemical vapor deposition oxide (HDP oxide) films are provided. According to various embodiments, the flowable oxide films may be used as a sacrificial layer and/or as a material for bottom up gap fill. In certain embodiments, the top surface of the filled gap is an HDP oxide film. The resulting filled gap may be filled only with HDP oxide film or a combination of HDP oxide and flowable oxide films. The methods provide improved top hat reduction and avoid clipping of the structures defining the gaps.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: May 20, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Kaihan Ashtiani, Michael Wood, John Drewery, Naohiro Shoda, Bart van Schravendijk, Lakshminarayana Nittala, Nerissa Draeger
  • Patent number: 8685867
    Abstract: Provided herein are novel pre-metal dielectric (PMD) integration schemes. According to various embodiments, the methods involve depositing flowable dielectric material to fill trenches or other gaps between gate structures in a front end of line (FEOL) fabrication process. The flowable dielectric material may be partially densified to form dual density filled gaps having a low density region capped by a high density region. In certain embodiments, the methods include further treating at least a portion of the gap fill material after subsequent process operations such as chemical mechanical planarization (CMP) or contact etching.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: April 1, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Michal Danek, Bart van Schravendijk, Nerissa Draeger, Lakshminarayana Nittala
  • Publication number: 20130230987
    Abstract: Provided herein are integration-compatible dielectric films and methods of depositing and modifying them. According to various embodiments, the methods can include deposition of flowable dielectric films targeting specific film properties and/or modification of those properties with an integration-compatible treatment process. In certain embodiments, methods of depositing and modifying flowable dielectric films having tunable wet etch rates and other properties are provided. Wet etch rates can be tuned during integration through am integration-compatible treatment process. Examples of treatment processes include plasma exposure and ultraviolet radiation exposure.
    Type: Application
    Filed: June 11, 2012
    Publication date: September 5, 2013
    Inventors: Nerissa Draeger, Karena Shannon, Bart van Schravendijk, Kaihan Ashtiani
  • Patent number: 8278216
    Abstract: The present invention provides methods of selectively depositing refractory metal and metal nitride cap layers onto copper lines inlaid in a dielectric layer. The methods result in formation of a cap layer on the copper lines without significant formation on the surrounding dielectric material. The methods typically involve exposing the copper lines to a nitrogen-containing organo-metallic precursor and a reducing agent under conditions that the metal or metal nitride layer is selectively deposited. In a particular embodiment, an amino-containing tungsten precursor is used to deposit a tungsten nitride layer. Deposition methods such as CVD or ALD may be used.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: October 2, 2012
    Assignee: Novellus Systems, Inc.
    Inventors: Glenn Alers, Nerissa Draeger, Michael Carolus, Julie Carolus, legal representative