Abstract: A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.

Abstract: The present invention provides a metal stack structure that stabilizes the flatband voltage and threshold voltages of material stacks that include a Si-containing conductor and a Hf-based dielectric. This present invention stabilizes the flatband voltages and the threshold voltages by introducing a rare earth metal-containing layer into the material stack that introduces, via electronegativity differences, a shift in the threshold voltage to the desired voltage. Specifically, the present invention provides a metal stack comprising a hafnium-based dielectric; a rare earth metal-containing layer located atop of, or within, said hafnium-based dielectric; an electrically conductive capping layer located above said hafnium-based dielectric; and a Si-containing conductor.

Abstract: A semiconductor structure is provided that includes a Vt stabilization layer between a gate dielectric and a gate electrode. The Vt stabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a targeted value and comprises a nitrided metal oxide, or a nitrogen-free metal oxide, with the proviso that when the Vt stabilization layer comprises a nitrogen-free metal oxide, at least one of the semiconductor substrate or the gate dielectric includes nitrogen. The present invention also provides a method of fabricating such a structure.

Abstract: The present invention provides a semiconductor structure comprising a semiconductor substrate having source and drain diffusion regions located therein, the source and drain diffusion regions being separated by a device channel; and a gate stack located on top of the device channel, the gate stack comprising a high-k gate dielectric, an insulating interlayer and a fully silicided metal gate conductor, the insulating interlayer located between the high-k gate dielectric and the fully silicided metal gate conductor, wherein the insulating interlayer is capable of stabilizing threshold voltage and flatband voltage of the semiconductor structure to a targeted value.

Abstract: A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.

Abstract: A method (and resultant structure) of forming a semiconductor structure, includes processing an oxide to have a crystalline arrangement, and depositing an amorphous semiconductor layer on the oxide by one of evaporation and chemical vapor deposition (CVD).

Abstract: An insulating interlayer for use in complementary metal oxide semiconductor (CMOS) that prevents unwanted shifts in threshold voltage and flatband voltage is provided. The insulating interlayer is located between a gate dielectric having a dielectric constant of greater than 4.0 and a Si-containing gate conductor. The insulating interlayer of the present invention is any metal nitride, that optionally may include oxygen, that is capable of stabilizing the threshold and flatband voltages. In a preferred embodiment, the insulating interlayer is aluminum nitride or aluminum oxynitride and the gate dielectric is hafnium oxide, hafnium silicate or hafnium silicon oxynitride. The present invention is particularly useful in stabilizing the threshold and flatband voltage of p-type field effect transistors.

Abstract: A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and is disposed under the gate electrode. The insulating material can be provided either as a layer or distributed within a gate dielectric material disposed under the gate electrode.

Abstract: A method (and resultant structure) of forming a semiconductor structure, includes forming a mixed rare earth oxide on silicon. The mixed rare earth oxide is lattice-matched to silicon.

Abstract: A structure (e.g., field effect transistor) and a method for making the structure, include a substrate having a source region, a drain region, and a channel region therebetween, an insulating layer disposed over the channel region, the insulating layer including a layer including aluminum nitride disposed over the channel region, and a gate electrode disposed over the insulating layer.

Abstract: A data storage element (and method of forming the same) includes a substrate comprising a semiconductor material, a metal oxide layer including an electrically insulating rare earth metal oxide disposed upon a surface of the substrate, a conductive material disposed upon the metal oxide layer, a first electrode electrically connected to the conductive material, and a second electrode connected to the substrate.