Abstract: Systems for time-deterministic, distributed and synchronized execution for control, test and measurement applications, consisting of one or more modules (M0, . . . , Mn) that share at least one trigger signal and one clock signal and comprising a Time-Deterministic Processor, which uses the clock signal and one or more of the trigger signals shared by all modules (M0, . . . , Mn) to run a program distributed across multiple modules (M0, . . . , Mn) with precise control of instant of execution of each instruction and synchronize the execution of all or a subset of modules (M0, . . . , Mn). The Time-Deterministic Processor communicates with a common signal bus to all modules (M0, . . . , Mn), comprising a control bus which share at least a clock and trigger signals. Optionally, the signal bus includes a communication bus with which the time-deterministic processor in the modules (M0, . . . , Mn) communicates with each other and optionally with a host processor or external computer.

Abstract: Systems for time-deterministic, distributed and synchronized execution for control, test and measurement applications, consisting of one or more modules (M0, . . . , Mn) that share at least one trigger signal and one clock signal and comprising a Time-Deterministic Processor, which uses the clock signal and one or more of the trigger signals shared by all modules (M0, . . . , Mn) to run a program distributed across multiple modules (M0, . . . , Mn) with precise control of instant of execution of each instruction and synchronize the execution of all or a subset of modules (M0, . . . , Mn). The Time-Deterministic Processor communicates with a common signal bus to all modules (M0, . . . , Mn), comprising a control bus which share at least a clock and trigger signals. Optionally, the signal bus includes a communication bus with which the time-deterministic processor in the modules (M0, . . . , Mn) communicates with each other and optionally with a host processor or external computer.

Abstract: A system of hardware configuration of a programmable control instrument, test and measure that includes an integrated FPGA is disclosed. The FPGA includes a static section comprising at least one static logic FPGA preset; a dynamic section comprising at least one dynamic logic FPGA programmable by a user; and a logical interface that connects the static section and dynamic section.

Abstract: A system of hardware configuration of a programmable control instrument, test and measure that includes an integrated FPGA is disclosed. The FPGA includes a static section comprising at least one static logic FPGA preset; a dynamic section comprising at least one dynamic logic FPGA programmable by a user; and a logical interface that connects the static section and dynamic section.

Abstract: System deterministic execution time, distributed and synchronized control applications, test and measurement. System synchronized distributed deterministic execution time for modules (M0, . . . , Mn) control, test and measurement that share at least one trigger signal and a clock signal and comprising a deterministic processor time, using the clock signal and one or more of the trigger signals shared by all modules (M0, . . . , Mn) to run a program distributed modules (MO, . . . , Mn) with precise control the moment of execution of each instruction and synchronize the execution of all or part of the set of modules (M0, . . . , Mn). The time deterministic processor communicates with a common signal bus to all (M0, . . . , Mn) modules, comprising a control bus which share the clock and trigger signals. Optionally, the signal bus includes a communication bus with which the time deterministic processor and the (M0, . . . , Mn) communicates modules together and optionally with a processor or external computer.