Abstract: A monolithically integrable spiral balun comprises a substrate having first, second, third, and fourth transmission lines formed thereon. The first transmission line has a first end coupled to receive an input signal and has a second end. The first transmission line forms a spiral that winds in a first direction from its first end to its second end. The second transmission line has a first end and has a second end electrically coupled to the second end of the first transmission line. The second transmission line forms a second spiral that winds in a second direction from its first end to its second end. The third transmission line has a first end for providing a first output and a second end for coupling to a first potential. The third transmission line forms a third spiral that interleaves the first spiral and winds in the second direction from its first end to its second end. A fourth transmission line has a first end for providing a second output and a second end for coupling to a second potential.

Abstract: A monolithically integrable spiral balun comprises a substrate having first, second, third, and fourth transmission lines formed thereon. The first transmission line has a first end coupled to receive an input signal and has a second end. The first transmission line forms a spiral that winds in a first direction from its first end to its second end. The second transmission line has a first end and has a second end electrically coupled to the second end of the first transmission line. The second transmission line forms a second spiral that winds in a second direction from its first end to its second end. The third transmission line has a first end for providing a first output and a second end for coupling to a first potential. The third transmission line forms a third spiral that interleaves the first spiral and winds in the second direction from its first end to its second end. A fourth transmission line has a first end for providing a second output and a second end for coupling to a second potential.

Abstract: Microelectromechanical (MEMS) devices are integrated with high frequency devices on a monolithic substrate or wafer. High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. MEMS devices, such as a switch, a variable capacitance device or a temperature control structure, are formed in the base monocrystalline substrate. High frequency devices, such as transistors or diodes, are formed in the overlaying layer of monocrystalline materials.

Abstract: Controlling and controlled components are integrated on a monolithic device. High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Abstract: Power combining amplifiers using two different monocrystalline materials in a monolithic device are provided. High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.