Patents by Inventor Neville A. Clark
Neville A. Clark has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10409935Abstract: Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload.Type: GrantFiled: April 11, 2016Date of Patent: September 10, 2019Assignee: Synopsys, Inc.Inventors: Neville A. Clark, James R. Torossian
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Patent number: 10360327Abstract: A method or apparatus for transforming a provided virtual processor model to a user virtual processor model. The method in on embodiment comprises transforming a virtual processor model to simulate a user target processor, by receiving a transformable virtual processor model having a transformable instruction set and a transformable pipeline, and transforming the transformable virtual processor model to a user virtual processor model designed to simulate a user target processor.Type: GrantFiled: June 16, 2015Date of Patent: July 23, 2019Assignee: Synopsys, Inc.Inventors: Neville A. Clark, James R. Torossian
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Publication number: 20190095547Abstract: Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload.Type: ApplicationFiled: April 11, 2016Publication date: March 28, 2019Inventors: Neville A. Clark, James R. Torossian
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Publication number: 20170293702Abstract: Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload.Type: ApplicationFiled: April 11, 2016Publication date: October 12, 2017Inventors: Neville A. Clark, James R. Torossian
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Patent number: 9311437Abstract: Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload.Type: GrantFiled: February 3, 2014Date of Patent: April 12, 2016Assignee: Synopsys, Inc.Inventors: Neville A. Clark, James R. Torossian
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Publication number: 20150310150Abstract: A method or apparatus for transforming a provided virtual processor model to a user virtual processor model. The method in on embodiment comprises transforming a virtual processor model to simulate a user target processor, by receiving a transformable virtual processor model having a transformable instruction set and a transformable pipeline, and transforming the transformable virtual processor model to a user virtual processor model designed to simulate a user target processor.Type: ApplicationFiled: June 16, 2015Publication date: October 29, 2015Inventors: Neville A. Clark, James R. Torossian
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Patent number: 9058447Abstract: A method of transforming a provided virtual processor model to a user virtual processor model. Also a tool, e.g., provided as instructions for operating in a host computer system for converting a provided virtual processor model to a user virtual processor model. Also a method of specifying one or more characteristics of a target processor to transform a provided virtual processor model to a user virtual processor model that when operating in a c-simulation system, simulates the operation of the target processor. For example, a method of specifying one or more characteristics of instructions to transform a provided virtual processor model to a user virtual processor model.Type: GrantFiled: June 10, 2013Date of Patent: June 16, 2015Assignee: Synopsys, Inc.Inventors: Neville A. Clark, James R. Torossian
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Publication number: 20140156249Abstract: Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload.Type: ApplicationFiled: February 3, 2014Publication date: June 5, 2014Applicant: Synopsys, Inc.Inventors: Neville A. Clark, James R. Torossian
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Patent number: 8644305Abstract: Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload.Type: GrantFiled: January 22, 2008Date of Patent: February 4, 2014Assignee: Synopsys Inc.Inventors: Neville A. Clark, James R. Torossian
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Publication number: 20130282358Abstract: A method of transforming a provided virtual processor model to a user virtual processor model. Also a tool, e.g., provided as instructions for operating in a host computer system for converting a provided virtual processor model to a user virtual processor model. Also a method of specifying one or more characteristics of a target processor to transform a provided virtual processor model to a user virtual processor model that when operating in a c-simulation system, simulates the operation of the target processor. For example, a method of specifying one or more characteristics of instructions to transform a provided virtual processor model to a user virtual processor model.Type: ApplicationFiled: June 10, 2013Publication date: October 24, 2013Inventors: Neville A. Clark, James R. Torossian
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Patent number: 8463589Abstract: A method of transforming a provided virtual processor model to a user virtual processor model. Also a tool, e.g., provided as instructions for operating in a host computer system for converting a provided virtual processor model to a user virtual processor model. Also a method of specifying one or more characteristics of a target processor to transform a provided virtual processor model to a user virtual processor model that when operating in a c-simulation system, simulates the operation of the target processor. For example, a method of specifying one or more characteristics of instructions to transform a provided virtual processor model to a user virtual processor model.Type: GrantFiled: July 30, 2007Date of Patent: June 11, 2013Assignee: Synopsys, Inc.Inventors: Neville A. Clark, James R. Torossian
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Patent number: 7567893Abstract: A simulation system, a computer product to implement a simulation method, and a method of simulating a digital circuit that has at least one element and at least one clock signal having clock attributes. The method includes maintaining a data structure for time-scheduled events scheduled to occur at particular simulation-times; and maintaining a data structure for clock-scheduled events each corresponding to a particular clock signal and scheduled to occur at a time that can be determined from at least one attribute of the clock signal, such that clocked-scheduled events are distinguishable from time-scheduled events, and such that each and every transition of any clock signal need not be scheduled in the time-scheduled event data structure.Type: GrantFiled: December 20, 2005Date of Patent: July 28, 2009Assignee: VaST Systems Technology CorporationInventors: James R. Torossian, Neville A. Clark
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Publication number: 20080319730Abstract: A method of transforming a provided virtual processor model to a user virtual processor model. Also a tool, e.g., provided as instructions for operating in a host computer system for converting a provided virtual processor model to a user virtual processor model. Also a method of specifying one or more characteristics of a target processor to transform a provided virtual processor model to a user virtual processor model that when operating in a c-simulation system, simulates the operation of the target processor. For example, a method of specifying one or more characteristics of instructions to transform a provided virtual processor model to a user virtual processor model.Type: ApplicationFiled: July 30, 2007Publication date: December 25, 2008Applicant: VAST SYSTEMS TECHNOLOGY CORPORATIONInventors: Neville A. Clark, James R. Torossian
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Publication number: 20080235415Abstract: Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload.Type: ApplicationFiled: January 22, 2008Publication date: September 25, 2008Applicant: VaST Systems Technology CorporationInventors: Neville A. CLARK, James R. Torossian
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Publication number: 20060149526Abstract: A simulation system, a computer product to implement a simulation method, and a method of simulating a digital circuit that has at least one element and at least one clock signal having clock attributes. The method includes maintaining a data structure for time-scheduled events scheduled to occur at particular simulation-times; and maintaining a data structure for clock-scheduled events each corresponding to a particular clock signal and scheduled to occur at a time that can be determined from at least one attribute of the clock signal, such that clocked-scheduled events are distinguishable from time-scheduled events, and such that each and every transition of any clock signal need not be scheduled in the time-scheduled event data structure.Type: ApplicationFiled: December 20, 2005Publication date: July 6, 2006Inventors: James Torossian, Neville Clark
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Patent number: 6562240Abstract: A method and apparatus for mixing a first material and a second material is described in which the first material comprises a mixture of two or more dissimilar components which it is desired to separate. The method and apparatus involve forming an intimate mixture of the two materials prior to separating the two dissimilar components of the first material. The apparatus involves the use of a hydrocyclone for aerating or gasifying a feed stream, such as waste water containing oleophilic residue or food residue, to entrain the particles of residue within the air or gas bubbles prior to separating the oil or food residues from the carrier material, typically water. Instead of using the hydrocyclone as a separator, it is used as a mixer which provides surprising results and facilitates separation of the aerated components.Type: GrantFiled: May 15, 2000Date of Patent: May 13, 2003Assignee: Separation Technologies Group Pty. Ltd.Inventor: Neville Clark
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Publication number: 20010018721Abstract: A processor upgrade on a card suitable to be interconnected with an industry standard PCI bus.Type: ApplicationFiled: May 3, 2001Publication date: August 30, 2001Inventors: Daniel McKenna, Neville Clark, Michael Thompson