Patents by Inventor Neville DIAS
Neville DIAS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10811751Abstract: Embodiments of the invention include an electromagnetic waveguide and methods of forming the electromagnetic waveguide. In an embodiment the electromagnetic waveguide includes a first spacer and a second spacer. In an embodiment, the first and second spacer each have a reentrant profile. The electromagnetic waveguide may also include a conductive body formed between in the first and second spacer, and a void formed within the conductive body. In an additional embodiment, the electromagnetic waveguide may include a first spacer and a second spacer. Additionally, the electromagnetic waveguide may include a first portion of a conductive body formed along sidewalls of the first and second spacer and a second portion of the conductive body formed between an upper portion of the first portion of the conductive body. In an embodiment, the first portion of the conductive body and the second portion of the conductive body define a void through the electromagnetic waveguide.Type: GrantFiled: December 30, 2016Date of Patent: October 20, 2020Assignee: Intel CorporationInventors: Rahul Ramaswamy, Chia-Hong Jan, Walid Hafez, Neville Dias, Hsu-Yu Chang, Roman Olac-Vaw, Chen-Guan Lee
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Patent number: 10763209Abstract: A MOS antifuse with an accelerated dielectric breakdown induced by a void or seam formed in the electrode. In some embodiments, the programming voltage at which a MOS antifuse undergoes dielectric breakdown is reduced through intentional damage to at least part of the MOS antifuse dielectric. In some embodiments, damage may be introduced during an etchback of an electrode material which has a seam formed during backfilling of the electrode material into an opening having a threshold aspect ratio. In further embodiments, a MOS antifuse bit-cell includes a MOS transistor and a MOS antifuse. The MOS transistor has a gate electrode that maintains a predetermined voltage threshold swing, while the MOS antifuse has a gate electrode with a void accelerated dielectric breakdown.Type: GrantFiled: August 19, 2014Date of Patent: September 1, 2020Assignee: Intel CorporationInventors: Roman Olac-Vaw, Walid Hafez, Chia-Hong Jan, Hsu-Yu Chang, Ting Chang, Rahul Ramaswamy, Pei-Chi Liu, Neville Dias
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Patent number: 10761264Abstract: Embodiments of the invention include an electromagnetic waveguide and methods of forming electromagnetic waveguides. In an embodiment, the electromagnetic waveguide may include a first semiconductor fin extending up from a substrate and a second semiconductor fin extending up from the substrate. The fins may be bent towards each other so that a centerline of the first semiconductor fin and a centerline of the second semiconductor fin extend from the substrate at a non-orthogonal angle. Accordingly, a cavity may be defined by the first semiconductor fin, the second semiconductor fin, and a top surface of the substrate. Embodiments of the invention may include a metallic layer and a cladding layer lining the surfaces of the cavity. Additional embodiments may include a core formed in the cavity.Type: GrantFiled: December 30, 2016Date of Patent: September 1, 2020Assignee: Intel CorporationInventors: Rahul Ramaswamy, Chia-Hong Jan, Walid Hafez, Neville Dias, Hsu-Yu Chang, Roman W. Olac-Vaw, Chen-Guan Lee
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Publication number: 20190356032Abstract: Embodiments of the invention include an electromagnetic waveguide and methods of forming the electromagnetic waveguide. In an embodiment the electromagnetic waveguide includes a first spacer and a second spacer. In an embodiment, the first and second spacer each have a reentrant profile. The electromagnetic waveguide may also include a conductive body formed between in the first and second spacer, and a void formed within the conductive body. In an additional embodiment, the electromagnetic waveguide may include a first spacer and a second spacer. Additionally, the electromagnetic waveguide may include a first portion of a conductive body formed along sidewalls of the first and second spacer and a second portion of the conductive body formed between an upper portion of the first portion of the conductive body. In an embodiment, the first portion of the conductive body and the second portion of the conductive body define a void through the electromagnetic waveguide.Type: ApplicationFiled: December 30, 2016Publication date: November 21, 2019Inventors: Rahul RAMASWAMY, Chia-Hong JAN, Walid HAFEZ, Neville DIAS, Hsu-Yu CHANG, Roman OLAC-VAW, Chen-Guan LEE
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Publication number: 20190278022Abstract: Embodiments of the invention include an electromagnetic waveguide and methods of forming electromagnetic waveguides. In an embodiment, the electromagnetic waveguide may include a first semiconductor fin extending up from a substrate and a second semiconductor fin extending up from the substrate. The fins may be bent towards each other so that a centerline of the first semiconductor fin and a centerline of the second semiconductor fin extend from the substrate at a non-orthogonal angle. Accordingly, a cavity may be defined by the first semiconductor fin, the second semiconductor fin, and a top surface of the substrate. Embodiments of the invention may include a metallic layer and a cladding layer lining the surfaces of the cavity. Additional embodiments may include a core formed in the cavity.Type: ApplicationFiled: December 30, 2016Publication date: September 12, 2019Inventors: Rahul RAMASWAMY, Chia-Hong JAN, Walid HAFEZ, Neville DIAS, Hsu-Yu CHANG, Roman W. OLAC-VAW, Chen-Guan LEE
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Patent number: 10192969Abstract: Semiconductor device(s) including a transistor with a gate electrode having a work function monotonically graduating across the gate electrode length, and method(s) to fabricate such a device. In embodiments, a gate metal work function is graduated between source and drain edges of the gate electrode for improved high voltage performance. In embodiments, thickness of a gate metal graduates from a non-zero value at the source edge to a greater thickness at the drain edge. In further embodiments, a high voltage transistor with graduated gate metal thickness is integrated with another transistor employing a gate electrode metal of nominal thickness. In embodiments, a method of fabricating a semiconductor device includes graduating a gate metal thickness between a source end and drain end by non-uniformly recessing the first gate metal within the first opening relative to the surrounding dielectric.Type: GrantFiled: August 19, 2014Date of Patent: January 29, 2019Assignee: Intel CorporationInventors: Chia-Hong Jan, Walid Hafez, Hsu-Yu Chang, Roman Olac-Vaw, Ting Chang, Rahul Ramaswamy, Pei-Chi Liu, Neville Dias
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Patent number: 10090304Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area. In further embodiments, the impurity source film may provide a source of dopant that renders the sub-fin region complementarily doped relative to a region of the substrate forming a P/N junction that is at least part of an isolation structure electrically isolating the active fin region from a region of the substrate.Type: GrantFiled: September 25, 2013Date of Patent: October 2, 2018Assignee: Intel CorporationInventors: Walid M. Hafez, Chia-Hong Jan, Jeng-Ya D. Yeh, Hsu-Yu Chang, Neville Dias, Chanaka Munasinghe
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Publication number: 20170207312Abstract: Semiconductor device(s) including a transistor with a gate electrode having a work function monotonically graduating across the gate electrode length, and method(s) to fabricate such a device. In embodiments, a gate metal work function is graduated between source and drain edges of the gate electrode for improved high voltage performance. In embodiments, thickness of a gate metal graduates from a non-zero value at the source edge to a greater thickness at the drain edge. In further embodiments, a high voltage transistor with graduated gate metal thickness is integrated with another transistor employing a gate electrode metal of nominal thickness. In embodiments, a method of fabricating a semiconductor device includes graduating a gate metal thickness between a source end and drain end by non-uniformly recessing the first gate metal within the first opening relative to the surrounding dielectric.Type: ApplicationFiled: August 19, 2014Publication date: July 20, 2017Inventors: Chia-Hong Jan, Walid Hafez, Hsu-Yu Chang, Roman Olac-Vaw, Ting Chang, Rahul Ramaswamy, Pei-Chi Liu, Neville Dias
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Publication number: 20170162503Abstract: A MOS antifuse with an accelerated dielectric breakdown induced by a void or seam formed in the electrode. In some embodiments, the programming voltage at which a MOS antifuse undergoes dielectric breakdown is reduced through intentional damage to at least part of the MOS antifuse dielectric. In some embodiments, damage may be introduced during an etchback of an electrode material which has a seam formed during backfilling of the electrode material into an opening having a threshold aspect ratio. In further embodiments, a MOS antifuse bit-cell includes a MOS transistor and a MOS antifuse. The MOS transistor has a gate electrode that maintains a predetermined voltage threshold swing, while the MOS antifuse has a gate electrode with a void accelerated dielectric breakdown.Type: ApplicationFiled: August 19, 2014Publication date: June 8, 2017Inventors: Roman OLAC-VAW, Walid HAFEZ, Chia-Hong JAN, Hsu-Yu CHANG, Ting CHANG, Rahul RAMASWAMY, Pei-Chi LIU, Neville DIAS
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Publication number: 20160211262Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area. In further embodiments, the impurity source film may provide a source of dopant that renders the sub-fin region complementarily doped relative to a region of the substrate forming a P/N junction that is at least part of an isolation structure electrically isolating the active fin region from a region of the substrate.Type: ApplicationFiled: September 25, 2013Publication date: July 21, 2016Inventors: Walid M. HAFEZ, Chia-Hong JAN, Jeng-Ya D. YEH, Hsu-Yu CHANG, Neville DIAS, Chanaka MUNASINGHE