Abstract: Disclosed is a vector indexed memory unit and method of operation. In one embodiment a plurality of values are stored in segments of a vector index register. Individual ones of the values are provided to an associated operator (e.g., adder or bit replacement). Individual ones of the operators operates on its associated vector index value and a base value to generate a memory address. These memory addresses are then concurrently accessed in one or more memory units. If the data in the memory units are organized as data tables, the apparatus allows for multiple concurrent table lookups. In an alternate embodiment, in addition to the above described operators generating multiple memory addresses, an adder is provided to add the base value to the value represented by the concatenation of the bits in the vector index register to generate a single memory address.

Abstract: Disclosed is a vector indexed memory unit and method of operation. In one embodiment a plurality of values are stored in segments of a vector index register. Individual ones of the values are provided to an associated operator (e.g., adder or bit replacement). Individual ones of the operators operates on its associated vector index value and a base value to generate a memory address. These memory addresses are then concurrently accessed in one or more memory units. If the data in the memory units are organized as data tables, the apparatus allows for multiple concurrent table lookups. In an alternate embodiment, in addition to the above described operators generating multiple memory addresses, an adder is provided to add the base value to the value represented by the concatenation of the bits in the vector index register to generate a single memory address.

Abstract: Disclosed is a vector indexed memory unit and method of operation. In one embodiment a plurality of values are stored in segments of a vector index register. Individual ones of the values are provided to an associated operator (e.g., adder or bit replacement). Individual ones of the operators operates on its associated vector index value and a base value to generate a memory address. These memory addresses are then concurrently accessed in one or more memory units. If the data in the memory units are organized as data tables, the apparatus allows for multiple concurrent table lookups. In an alternate embodiment, in addition to the above described operators generating multiple memory addresses, an adder is provided to add the base value to the value represented by the concatenation of the bits in the vector index register to generate a single memory address.

Abstract: A method includes providing a redundant array of inexpensive disks (RAID) array having at least a stripe sector unit (SSU) of data written to it. A request is received to perform a write operation to the RAID array beginning at a starting data storage address (DSA) that is not aligned with an SSU boundary. An alert is generated in response to the request.

Abstract: A method includes storing first and second sets of parameters in a register. Each set of parameters defines a storage transaction to store data to a computer readable medium or a retrieval transaction to retrieve data from the computer readable medium. The first storage or retrieval transaction is performed according to the first set of parameters. The second set of parameters is retrieved from the register automatically when the first storage or retrieval transaction is completed, without waiting for a further command from a control processor. The second storage or retrieval transaction is performed according to the retrieved second set of parameters. A system for performing the method and a computer readable medium containing pseudocode for generating an application specific integrated circuit that performs the method are provided.

Abstract: In a system having a control processor, an apparatus is provided with at least one memory. The at least one memory includes a first memory portion for storing at least one first decryption key. A decryption engine uses the first decryption key to decrypt information. A key processor provides the first decryption key to the decryption engine without allowing the control processor to access the first decryption key. A system incorporating the key processing apparatus and a method of using the apparatus are also provided.

Abstract: In one embodiment, a method for reading data from a storage-device array including three or more storage devices. The array has a plurality of sector levels, each sector level containing one sector on each storage device in the array at corresponding addresses across the storage devices. Each sector level includes (i) parity data stored on a first storage device and (ii) information stored on the two or more remaining storage devices. The parity data for a current sector level is generated from the information stored at the current sector level on the remaining storage devices.

Abstract: An apparatus and method are provided for extracting connection information from a traffic header in a communications network. The apparatus includes a first storage element containing a first look-up table for determining a first data packet header offset and data size for extracting a communications protocol type from the header and a second storage element containing a second look-up table for determining from the communications protocol type a second data packet header offset and second data size for extracting a connection address from the header. The storage elements may be in the form of content-addressable memories. Exception handling and hardware initialization can be controlled by a system processor.

Abstract: A method and apparatus are disclosed for allocating functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional very long instruction word architectures and conventional multithreaded architectures to reduce execution time within an individual program, as well as across a workload. The present invention utilizes instruction packet splitting to recover some efficiency lost with conventional multithreaded architectures. Instruction packet splitting allows an instruction bundle to be partially issued in one cycle, with the remainder of the bundle issued during a subsequent cycle. The allocation hardware assigns as many instructions from each packet as will fit on the available functional units, rather than allocating all instructions in an instruction packet at one time. Those instructions that cannot be allocated to a functional unit are retained in a ready-to-run register.

Abstract: A method and apparatus are disclosed for allocating functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional VLIW architectures and conventional multithreaded architectures to reduce execution time within an individual program, as well as across a workload. The present invention utilizes a compiler to detect parallelism. The disclosed multithreaded VLIW architecture exploits program parallelism by issuing multiple instructions, in a similar manner to single threaded VLIW processors, from a single program sequencer, and also supports multiple program sequencers, as in simultaneous multithreading. Instructions are allocated to functional units to issue multiple VLIW instructions to multiple functional units in the same cycle. The allocation mechanism of the present invention occupies a pipeline stage just before arguments are dispatched to functional units.

Abstract: To support IP routing table longest-prefix matching, a (ternary content-addressable) memory is managed by assigning its locations to interleaved pages and gaps. Each page has zero or more locations assigned to it, where all entries in a page have the same prefix length. Each gap has zero or more empty locations assigned to it. The pages are organized by descending prefix length. Associated with each page is a free-list identifying empty locations in that page. An “invariant” rule may dictate that first and last page locations cannot be empty. Whenever an entry is deleted from the first or last location in a page, that location is shifted (i.e., reassigned) to the adjacent gap. The direction chosen to search for an empty location for inserting a new entry is based on a global measure of the relative fullness of memory regions above and below the new entry's page.

Abstract: Disclosed is a vector indexed memory unit and method of operation. In one embodiment a plurality of values are stored in segments of a vector index register. Individual ones of the values are provided to an associated operator (e.g., adder or bit replacement). Individual ones of the operators operates on its associated vector index value and a base value to generate a memory address. These memory addresses are then concurrently accessed in one or more memory units. If the data in the memory units are organized as data tables, the apparatus allows for multiple concurrent table lookups. In an alternate embodiment, in addition to the above described operators generating multiple memory addresses, an adder is provided to add the base value to the value represented by the concatenation of the bits in the vector index register to generate a single memory address.

Abstract: A method and apparatus are disclosed for releasing functional units in a multithreaded very large instruction word (VLIW) processor. The functional unit release mechanism can retrieve the capacity lost due to multiple cycle instructions. The functional unit release mechanism of the present invention permits idle functional units to be reallocated to other threads, thereby improving workload efficiency. Instruction packets are assigned to functional units, which can maintain their state, independent of the issue logic. Each functional unit has an associated state machine (SM) that keeps track of the number of cycles that the functional unit will be occupied by a multiple-cycle instruction. Functional units do not reassign themselves as long as the functional unit is busy. When the instruction is complete, the functional unit can participate in functional unit allocation, even if other functional units assigned to the same thread are still busy.

Abstract: A method and apparatus are disclosed for allocating functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional very long instruction word (VLIW) architectures and conventional multithreaded architectures to reduce execution time within an individual program, as well as across a workload. The present invention utilizes instruction packet splitting to recover some efficiency lost with conventional multithreaded architectures. Instruction packet splitting allows an instruction bundle to be partially issued in one cycle, with the remainder of the bundle issued during a subsequent cycle. There are times, however, when instruction packets cannot be split without violating the semantics of the instruction packet assembled by the compiler. A packet split identification bit is disclosed that allows hardware to efficiently determine when it is permissible to split an instruction packet.