Patents by Inventor Nga Cheung

Nga Cheung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060074563
    Abstract: An applications programming interface is described that includes code libraries that enable transfer of pixel data, intermediate results data, or both, from a data structure or data file directly or indirectly to a user-provided application. The pixel data and intermediate results data may include data from biological experiments related probe arrays.
    Type: Application
    Filed: August 31, 2005
    Publication date: April 6, 2006
    Applicant: Affymetrix, INC.
    Inventors: Luis Jevons, Derek Bernhart, Nga Cheung, Conrad Sheppy
  • Patent number: 6119175
    Abstract: A communications unit configured to be implemented in an ASIC environment utilizes only a small amount of chip surface area and requires a minimum number of pins. The unit operates asynchronously with respect to the ASIC internal clock so that communications can occur independent of such internal clock. In one embodiment the communications unit includes a controller coupled to a shift register via a data bus. Pin connections to the controller include a request line REQ, an input/output control line I/O (or INOUT), an acknowledgement line ACK, an external clock line EXTCLK, and a data line DATA. The shift register also is coupled, via a data bus, to a memory module, e.g., a RAM. An ASIC processor is coupled to the controller, shift register and memory module via control lines.
    Type: Grant
    Filed: June 8, 1998
    Date of Patent: September 12, 2000
    Assignee: General Electric Company
    Inventors: Juka Mikko Hakkarainen, Nga Cheung Lee, Chung-Yih Ho
  • Patent number: 5799211
    Abstract: A communications unit configured to be implemented in an ASIC environment utilizes only a small amount of chip surface area and requires a minimum number of pins. The unit operates asynchronously with respect to the ASIC internal clock so that communications can occur independent of such internal clock. In one embodiment the communications unit includes a controller coupled to a shift register via a data bus. Pin connections to the controller include a request line REQ, an input/output control line I/O (or INOUT), an acknowledgement line ACK, an external clock line EXTCLK, and a data line DATA. The shift register also is coupled, via a data bus, to a memory module, e.g., a RAM. An ASIC processor is coupled to the controller, shift register and memory module via control lines.
    Type: Grant
    Filed: March 22, 1996
    Date of Patent: August 25, 1998
    Assignee: General Electric Company
    Inventors: Juka Mikko Hakkarainen, Nga Cheung Lee, Chung-Yih Ho